*** FACET tool-SimulateSPICE FROM LIBRARY samples ***
*** VERSION 1 LAST REVISED Thu Nov  4 09:46:36 1999
*** EXTRACTED BY ELECTRIC DESIGN SYSTEM, VERSION 6.02
*** UC SPICE *** , MIN_RESIST 50.000000, MIN_CAPAC 0.040000FF
.OPTIONS NOMOD NOPAGE
*CMOS/BULK-NWELL (PRELIMINARY PARAMETERS)
.OPTIONS NOMOD DEFL=3UM DEFW=3UM DEFAD=70P DEFAS=70P LIMPTS=1000
+ITL4=1000 ITL5=0 RELTOL=0.01 ABSTOL=500PA VNTOL=500UV LVLTIM=2
+LVLCOD=1
.MODEL N NMOS LEVEL=1
+KP=60E-6 VTO=0.7 GAMMA=0.3 LAMBDA=0.05 PHI=0.6
+LD=0.4E-6 TOX=40E-9 CGSO=2.0E-10 CGDO=2.0E-10 CJ=.2MF/M^2
.MODEL P PMOS LEVEL=1
+KP=20E-6 VTO=0.7 GAMMA=0.4 LAMBDA=0.05 PHI=0.6
+LD=0.6E-6 TOX=40E-9 CGSO=3.0E-10 CGDO=3.0E-10 CJ=.2MF/M^2
.MODEL DIFFCAP D CJO=.2MF/M^2

*** TOP LEVEL FACET: tool-SimulateSPICE{lay}
** POWER NET: power
** GROUND NET: 0 (ground)
** PIN 5: power (network: power)
** PIN 3: in (network: in)
** PIN 2: out (network: out)
Mnode12 0 3 2 0 N L=0.40U W=0.60U AS= 1.12P AD= 0.36P PS= 4.40U PD= 2.40U
Mnode11 2 3 5 5 P L=0.40U W=0.60U AS= 0.36P AD= 1.12P PS= 2.40U PD= 4.40U
** Extracted Parasitic Elements:
C1 3 0      0.28F
C2 2 0      0.22F
** Sources and special nodes:
Vnode5 3 0 PWL(0NS 0 3NS 0 4NS 5)
Vnode4 5 0 DC 5
.PRINT TRAN V(0) V(2)
.TRAN .2NS 7NS 0NS .2NS
.END
