/* Verilog for facet tool-SimulateVERILOG{sch} from Library samples */
/* Created on Fri Apr  2 09:59:22 1999 */
/* Last revised on Thu Sep 21 10:35:14 2000 */
/* Written on Fri Dec  1 08:57:53 2000 by Electric VLSI Design System, version 6.02 */

module tool_SimulateVERILOG(a, m, z);
  input a;
  input [0:3] m;
  input [0:3] z;

  wire ImpInv1;
  wire [0:3] d;
  wire net1;

  /* user-specified Verilog declarations */
  wire b, c;
  wire e, f;

  /* user-specified Verilog code */
  a = b + c;
  b = e - f;

  /* automatically generated Verilog */
  xor node5(z[0], z[3], a);
  inv Imp1 (ImpInv1, z[2]);
  or node3(net1, z[3], a, ImpInv1);
  not node4(z[1], net1);
  and node7_0(d[0], z[0], m[0]);
  and node7_1(d[1], z[1], m[1]);
  and node7_2(d[2], z[2], m[2]);
  and node7_3(d[3], z[3], m[3]);
endmodule   /* tool_SimulateVERILOG */
