Using Electric 12-10: The Tools Menu

Chapter 12: MENU SUMMARY

| ## 12-10: The Tools Menu |

This menu is a collection of submenus that controls the different analysis and synthesis tools in Electric. For analysis, there are Design-Rule Checkers, a simulator, many simulation interfaces, and a network consistency checker. For synthesis, there are routers, PLA generators, a VHDL compiler, and a silicon compiler place-and-route system.

### DRC [9-2]

| This submenu controls the design-rule checkers. There is an incremental system which watches all design and displays warnings where appropriate. There are also two hierarchical checkers and an interface to the Dracula DRC system.

| Hierarchical Check | This checks the current facet hierarchically (all geometry is checked, all the way down the hierarchy).
| Hierarchical Check Selection | This checks the current facet hierarchically, but only in the selected area.
| Check this Level Only | This command checks the current facet nonhierarchically (only geometry in the current facet is checked, not in any subfacets).
| DRC Options... | This command lets you control a number of DRC options, including whether or not the incremental DRC is running, whether to interactively highlight errors, and more.
| DRC Rules... | This command provides a way to examine and modify the design rules (by using the "For layer" and "To layer" areas).
| Clear Ignored Errors | This command tells the design-rule checker to throw away the list of ignored errors that may have accumulated.
| Write Dracula Deck | This command tells the design-rule checker to produce an input deck for the Dracula design-rule checker. At the current time, only layout in the MOSIS CMOS (mocmos) technology can be checked in this manner. However, with the "Edit Dracula Deck" button of the DRC Options... dialog, rule sets may be defined for any technology.
| Old Hierarchical Check | This checks the current facet hierarchically, using an older, slower algorithm. It is retained because the current hierarchical checker is too new and not thoroughly tested.
| Old Hierarchical Check Selection | This checks the current facet hierarchically, using the old algorithm, and only in the selected area.

### Simulation (Built-in) [10-1] [10-2]

| This submenu controls the gate-level simulator in Electric. Electric comes with a simulator called ALS (Asynchronous Logic Simulator), but you can also add an IRSIM engine. You can control simulation, move up and down the hierarchy, control test vectors, and set simulation parameters.

| Simulate... | This command causes the current facet to be simulated. If the current facet is not a netlist, and the netlist associated with this facet is missing or out of date, the VHDL compiler is invoked to build a new one. If the current facet is not VHDL, and the VHDL associated with this facet is missing or out of date, it is generated from the schematic or layout. A waveform display is normally shown for viewing signal values.
| Simulation Options... | This command presents a dialog for control of simulation parameters. The simulation engine can be selected (initially, Electric comes with only the ALS simulator, but a built-in IRSIM engine is available from Static Free Software. The "Resimulate each change" item causes each change that is made to something being simulated to trigger resimulation and display of the results. The "Auto advance time" item tells the simulator to move the time cursor automatically when a new signal is added to the simulation. The "Multistate display" check tells the simulator to show signals in the layout or schematics window with texturing and color to indicate strength. Without this, a simple on/off indication is drawn in the layout or schematics window. The "Show waveform window" check tells the simulator to create a separate window with waveform plots when simulation starts. The waveform window can be cascaded (a separate overlapping window) or tiled (placed in one half of the original circuit's window). The radix of bus signals in the waveform window can be selected. For ALS, the maximum number of events to simulate can be changed if you want to extend the simulator's range (and memory usage). For IRSIM, the level of parasitics and the file of parasitic information can be specified.
| Transistor Strength |
| This command lets you change the strength of the selected transistor.
| Annotate Delay Data (ALS) |
| This command lets you select which of the sets of stimulus data to use for the ALS simulator. The stimulus data is acquired with the SDF subcommand of the Import command of the File menu.
| Restore Signal Display Order (ALS) | This command restores the default set of signals in the waveform display, which is useful if they have been rearranged or if some signals were deleted. It only works for the ALS simulator.
| Down Hierarchy... | This command causes the simulation to descend the hierarchy to a lower level so that signals can be viewed there. You will be prompted with a list of lower levels to view.
| Up Hierarchy | This command causes the simulation to ascend to the next higher level of hierarchy.
| Read Vectors from Disk | This command causes a file of test vectors to be read from disk. You will be prompted for the file name.
| Save Vectors to Disk | This command causes the current set of test vectors to be saved to disk. You will be prompted for the file name.
| Save Fectors as SPICE commands | This command exports the current set of test vectors as a SPICE deck.
| Clear All Vectors | This command erases all test vectors from the simulation.

### Simulation (SPICE) [9-4]

| This submenu controls the SPICE simulator, including deck generation and plotting SPICE output.

| Write SPICE Deck | This command generates an input deck for the SPICE circuit-level simulator. Because SPICE is not an interactive system, it is necessary to specify inputs and outputs in the circuit. This is done by placing Source and Meter components (from the New Analog Component submenu of the Edit menu), parametrizing them with the actual SPICE message, and connecting them to the circuitry. It is also necessary to specify Transient or DC analysis by placing an appropriate Source component in the facet.
| SPICE Options... | This command allows many SPICE options to be controlled, for example, the SPICE format (SPICE 2, SPICE 3, HSPICE, or PSPICE); control of parasitics in the deck; control of SPICE execution (UNIX systems only); control of header, trailer, and individual facet model cards; and much more.
| Plot SPICE Listing | This command reads the output of a SPICE run and shows the signals in a waveform window.
| Add SPICE Card | This command allows you to click in the design and type a SPICE card that will be inserted into the generated deck.
| Set SPICE Template | This command allows you to create a SPICE template when defining new primitives.
| Set SPICE Model... | This command allows you to change the SPICE model of the currently selected node.

### Simulation (Verilog) [9-4]

| This submenu controls the generation of Verilog simulation netlists.

| Write Verilog Deck | This command generates an input deck for the Verilog simulator.
| Verilog Options... | This command generates displays a dialog for controlling Verilog deck generation.
| Set Verilog Wire | This command lets you set the type of Verilog wire that the current arc will produce (either Wire, Trireg, or Default). The Default option uses the setting from the Verilog Options... dialog.
| Add Verilog Declaration | This command allows you to click in the design and type Verilog declarations that will be inserted into the generated deck.
| Add Verilog Code | This command allows you to click in the design and type Verilog code that will be inserted into the generated deck.
| Set Verilog Template | This command allows you to create a Verilog template when defining new primitives.

### Simulation (Others) [9-4]

| This submenu allows input decks to be written for many different simulators.

| FastHenry Arc Info... |
This command presents a dialog for including the currently selected arc in the FastHenry analysis, and for setting options on that arc. You can override the thickness, set the number of subdivisions, set the analysis group, and even set a height for the two arc ends. |
| Write FastHenry Deck... | This command generates a FastHenry deck from the current facet.
| FastHenry Options... | This command presents a dialog of options for FastHenry deck generation. The frequency and multipole options control flags that are placed in the deck. The default thickness and subdivision fields provide values that are used when no overrides are specified for individual arcs.
| Write IRSIM Deck | This command generates an input deck for the IRSIM switch-level simulator.
| Write ESIM Deck | This command generates an input deck for the ESIM switch-level simulator (nMOS only, no timing).
| Write RSIM Deck | This command generates an input deck for the RSIM switch-level simulator (nMOS only).
| Write RNL Deck | This command generates an input deck for the RNL switch-level simulator (nMOS only, Lisp-like interface).
| Write COSMOS Deck | This command generates an input deck for the COSMOS switch-level simulator (MOS only).
| Write MOSSIM Deck | This command generates an input deck for the MOSSIM switch-level simulator (MOS only).
| Write TEGAS Deck | This command generates an input deck for the TEGAS/TEXSIM gate-level simulator.
| Write SILOS Deck | This command generates an input deck for the SILOS simulator.
| Write PAL Deck | This command generates an input deck for the Abel PAL generator/simulator.

### Electrical Rules [9-3]

| These commands do static analysis of the circuit, which include well analysis and antenna rules.

| Analyze Wells | This command examines the current facet and checks all well areas for proper electrical rules. The farthest distance from a well contact to the edge of its implant is shown.
| Well Check Options... | This presents a dialog with Well and Substrate Checking options. You can choose to require one contact per area, or only one contact anywhere on the chip. You can also check for proper power and ground connections.
| Antenna-Rules Check | This command examines the current facet and all below it for antenna rules violations. Antenna rules ensure that there is no path from a large area of metal or poly to a small number of transistor gates.
| Antenna-Rules Options... | This presents a dialog with Antenna rule ratio limits.

### Network [6-9] [9-6]

| This submenu controls miscellaneous network functions, including a Network Consistency Checking (NCC) facility. Some systems call network consistency checking "LVS" (Layout vs. Schematic), but Electric uses the term NCC because it can compare any two facets, not just layout vs. schematic.

| Show Network | This command shows the equivalent to the currently highlighted network in all other windows. It also works for network names seleted in a text window. If this facet has been run through the network consistency checker, that information will be used.
| NCC Control and Options... | This presents a dialog for controlling the network consistency checker. On top are the two facets whose networks are to be compared. If there are two facets currently being displayed, they are loaded into these fields. The lower portion controls the NCC process. On the left are the NCC controls, and on the right half are per-facet overrides of some of these settings. The bottom has buttons for running NCC or Preanalysis.
| Node Extract [7-3] | This command extracts connectivity from a facet that has only geometry (pure-layer nodes). Such facets are the result of reading external format files, such as CIF and GDS. The pure-layer nodes are removed and replaced with a connected network of nodes and arcs. Unfortunately, the node extractor is only partially implemented and should not be counted-on to properly extract. Also, it does not recognize transistors.
| Network Options... | This presents a dialog for controlling the network tool. The top part controls network numbering options. "Unify Power and Ground" indicates that all power and ground ports should be considered to be electrically tied, regardless of their connectivity in the circuit. When not checked, this happens only in schematics, where the Power and Ground nodes appear.
"Unify all like-named nets" indicates that all networks with the same name are to be unified, regardless the nature of the circuit. When not checked, only schematic facets have like-named networks electrically connected. "Ignore Resistors" requests that resistors be treated like wires when determining networks. |
The lower part of the dialog controls how busses will be numbered when they are not explicitly defined. You can choose to start them at 0 or 1, and can choose to order them ascending or descending.
| Show Power and Ground | This command highlights all of the power and ground networks in the current facet.
| Rip Bus Signals [7-6] | This command takes the currently selected bus wire and adds wire taps for each signal on the bus. The wires run perpendicular to the bus and are labeled with their signal.
| Redo Network Numbering [6-12] | This command is not generally needed but may be useful if you suspect that the network information is incorrect.

### Logical Effort [9-12]

| This command does Logical Effort analysis, which determines the transistor ratios to use in digital schematic components in order to get optimal circuit speed.

| Analyze Facet | This command examines the current facet and annotates all schematic gates with fanout information.
| Analyze Path | This command examines the circuitry between the two highlighted components and annotates the gates with fanout information.
| New Arc Load | This command creates a special "load" symbol that has capacitance and can connect to the circuit to declare a load there. The capacitance value can be changed by double-clicking and typing a new value.
| Set Node Effort... | This command allows you to set an overriding logical effort value on the currently selected node. This value can be changed by double-clicking and typing a new value.
| Logical Effort Options... | This command provides options for controlling the Logical Effort tool.
The Maximum Stage Gain is used in the Analyze Facet command. The "Display intermediate capacitances" enables the display of capacitance values on arcs in the circuit. The "Highlight components" causes the tool to highlight the active components that it is analyzing. |
Finally, the dialog lets you set the wire ratio for each arc (a value used in load computation).
| Estimate Delays | This command examines each network in the circuit and calculates load factors. It is not generally useful, and applies to Logical Effort calculations.
| Show Network Loads | This command lists every network in the current facet, showing the wire length, load, and other information.
| Analyze Network | This command shows a detailed analysis of the currently selected network, including the area and perimeter information for each layer, as well as load information.

### Routing [9-5]

| This submenu controls a number of wire routing facilities.

| Enable Auto-Stitching | This command instructs the router to watch all subsequent layout activity and to place arcs wherever touching nodes create implicit connections. It is useful to issue this command before generating arrays, because the array may produce many implicit connections that this router will make explicit. The menu entry changes to Stop Auto-Stitching to disable the function.
| Auto-Stitch Highlighted Now | This does auto-stitching only in the currently highlighted area. The highlighted area is defined as the bounding rectangle of everything that is highlighted. A more precise way of defining a highlighted area is to use the rectangle select button to drag a rectangle on the screen.
| Enable Mimic-Stitching | This command instructs the router to watch all subsequent layout activity and to automatically create other arcs in similar locations whenever you create one by hand. The menu entry changes to Disable Mimic-Stitching to disable this function.
| Mimic-Stitching Now | This command instructs the router to mimic the last arc that was created. It is not necessary for the Mimic Stitcher to be enabled.
| Maze-Route Selected | This command runs the maze router in the selected area. All occurrences of the Unrouted wire will be replaced with real geometry.
| Maze-Route Facet | This command runs the maze router in the current facet. All occurrences of the Unrouted wire will be replaced with real geometry.
| River-Route | This command runs the river-router in the current facet. All occurrences of the Unrouted wire will be replaced with real geometry.
| Routing Options... | This command provides a dialog for control of the stitching routers.
For the Auto-Stitcher, you can select the type of arc to use (the default is to automatically determine the arc type to use from the ports). |
For the Mimic-Stitcher, you can instruct it to mimic wire deletions as well as creations. The Mimic-Stitcher can also be instructed to relax its rules for mimicing (by default, arcs are mimiced if they run between the same ports on other nodes; however you can request that mimicing happens between any other ports that are the same distance apart as the original arc).
| Unroute | This command takes the currently selected network(s) and converts them to unrouted wires. After this command, you can maze-route or river-route the unrouted wires.
| Get Unrouted Wire | The Unrouted wire of the Generic technology is used to define routing requirements (see Section 7-9). This command selects the Generic arc so that subsequent wiring commands will use it. This is necessary in order to do maze and river-routing.
| Copy Routing Topology | This command remembers the network of connections in the current facet for subsequent creation in another facet (specified with Paste Routing Topology).
| Paste Routing Topology | This command examines the current facet and compares its network to the one that was copied (with Copy Routing Topology). Where there are missing connections in this facet, the command creates Unrouted arcs to connect them.

### Generation

| This command provides a pad frame generator and two PLA generators. All will run faster if the design-rule checker is turned off first.

| Pad Frame [9-8] | This command prompts for a disk file that describes the placement of pads around a core facet. The file includes information about the library that contains the pads and also the connection between the pads and ports on the core facet.
| nMOS PLA [9-7] | This command prompts for a personality table and generates nMOS layout, complete with power and clocking. See the description of the PLA generator for a sample personality table.
| MOSIS CMOS PLA [9-7] | This command prompts for two personality tables: the AND and the OR tables. It also offers options about the location of inputs and outputs. See the description of the PLA generator for a sample CMOS personality table.

### VHDL Compiler [9-10]

| This submenu provides direct control of the VHDL compiler, which translates VHDL textual descriptions into netlists. Besides controlling which format netlist is generated, it is also possible to determine whether the netlist of the VHDL is to be stored in memory (in a facet) or on disk.

| Compile for Silicon Compiler | This command causes the VHDL in the current facet to be compiled into a netlist for the silicon compiler. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.sci" is written.
| Compile for Simulation | This command causes the VHDL in the current facet to be compiled into a netlist for simulation. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.net" is written.
| Compile for RNL | This command causes the VHDL in the current facet to be compiled into a RNL simulator netlist. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.net" is written.
| Compile for RSIM | This command causes the VHDL in the current facet to be compiled into a RSIM simulator netlist. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.net" is written.
| Compile for SILOS | This command causes the VHDL in the current facet to be compiled into a SILOS simulator netlist. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.sil" is written.
| VHDL Options... |
This command provides options for controlling whether the VHDL or the Netlist are stored in memory or on disk. Besides the compile subcommands in this menu, the state of these switches also affects the Make VHDL View command of the View menu, the Simulate... subcommand of the Simulation (Built-in) command of the Tools menu, and the Get Network for Current Facet subcommand of the Silicon Compiler command of the Tools menu. |
This command also controls the VHDL that is generated from schematics nodes. Each schematics node is shown, along with its regular and negated VHDL symbol (the use of "%d" is replaced by the number of inputs on the gate).
| Select Behavioral Library... | When compiling for simulation, behavioral models will be included if they are found in the current library. This command allows an alternate library to be searched for the models. Note that each model can be found in the "netlist-als-format" view of an appropriately named cell.

### Silicon Compiler [9-9]

| This submenu is an extensive system for placing and routing standard cell libraries from a structural VHDL description. Simply run each command in sequence: select a library, set options, obtain a netlist, place, route, and make Electric layout.

| Read MOSIS CMOS Library | This command requests that the MOSIS CMOS standard cell library be used. This cell library is not guaranteed to be correct and exists only for illustration purposes. See the "Silicon Compiler" section of Chapter 9 for a description of the cells in this library.
| Silicon Compiler Options... | This command presents a dialog that allows the setting of various parameters for the silicon compilation process.
| Get Network for Current Facet | This command gets a netlist for the current facet. If the current facet is not a netlist, and the netlist associated with this facet is missing or out of date, the VHDL Compiler will be used to create a netlist. If the current facet is not VHDL, and the VHDL associated with this facet is missing or out of date, the VHDL will be generated from a schematic.
| Do Placement | This command computes the placement of standard cells.
| Do Routing | This command computes the routing among the placed standard cells.
| Make Electric Layout | This command generates final circuitry from the computed placement and routing. The design-rule checker is turned off during this step.
| Issue Special Instructions... | This command allows you to communicate directly with the Silicon Compiler. Only those familiar with the system should do this (the other commands in this submenu handle standard functions without the need to know how the compiler works).

### Compaction [9-11]

| This submenu controls the layout compactor.

| Do Compaction | This command compacts the layout in the current window to design-rule distances, using single-axis compaction. It alternates horizontal and vertical compaction until no additional space can be saved. Compaction is done downward and to the left.
| Compact Horizontally | This command instructs the compactor to compact the current facet one time in the horizontal direction.
| Compact Vertically | This command instructs the compactor to compact the current facet one time in the vertical direction.
| Compaction Options... |
This command presents a dialog that allows you to tell the compactor to spread the circuit where it is too close for the design rules. You can also request information about the compaction process. |

### List Tools [9-1]

This command lists all of the tools, showing which ones are active.

### Language Interpreter [11-1]

| There are language interpreters in Electric: TCL, LISP, and Java. The interpreters can be activated with the subcommands here. Once activated, you communicate with them in the messages window. Note that, because of copyright restrictions, the LISP interpreter is not part of the standard GNU distribution and must be obtained separately from Static Free Software. The TCL and Java interpreters must also be obtained separately. See the installation instructions for UNIX, Section 1-3, Macintosh, Section 1-4, and Windows, Section 1-5.

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