/* 
 * Copyright (c) 1995-1994 The University of Utah and
 * the Computer Systems Laboratory at the University of Utah (CSL).
 * All rights reserved.
 *
 * Permission to use, copy, modify and distribute this software is hereby
 * granted provided that (1) source code retains these copyright, permission,
 * and disclaimer notices, and (2) redistributions including binaries
 * reproduce the notices in supporting documentation, and (3) all advertising
 * materials mentioning features or use of this software display the following
 * acknowledgement: ``This product includes software developed by the
 * Computer Systems Laboratory at the University of Utah.''
 *
 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
 * IS" CONDITION.  THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * CSL requests users of this software to return to csl-dist@cs.utah.edu any
 * improvements that they make and grant CSL redistribution rights.
 *
 *      Author: Bryan Ford, University of Utah CSL
 */
#ifndef _I386_IDT_
#define _I386_IDT_

#include <mach/vm_param.h>
#include <mach/machine/seg.h>

#include "irq.h"

/* On a standard PC, we only need 16 interrupt vectors,
   because that's all the PIC hardware supports.  */
#ifndef IDTSZ
#define IDTSZ (IDT_IRQ_BASE+IRQ_COUNT)
#endif


/* Fill a gate in a CPU's IDT.  */
#define fill_idt_gate(cpu, int_num, entry, selector, access) \
	fill_gate(&(cpu)->tables.idt[int_num],				\
		  entry, selector, access, 0)

#endif _I386_IDT_
