#include #include #include struct net_local { int pad; #ifdef __KERNEL__ struct enet_statistics stats; #endif ushort len, other_len; ushort pac_cnt_in_tx_buf, saved_tx_size; uint tx_unit_busy:1, fixoverflow:1, data_mode:4; uint addr_mode; /* Current mode of the adaptor (promiscuous or not). */ }; struct rx_header { short pad; short rx_count; char rx_status; char pad1; short pad2; }; #define DATA 0 #define STATUS 1 #define CONTROL 2 #define Ctrl_LNibRead 0x08 /* LP_PSELECP */ #define Ctrl_HNibRead 0 #define Ctrl_LNibWrite 0x08 /* LP_PSELECP */ #define Ctrl_HNibWrite 0 #define Ctrl_SelData 0x04 /* LP_PINITP */ #define Ctrl_IRQEN 0x10 /* LP_PINTEN */ #define EOW 0xE0 #define EOC 0xE0 #define WrAddr 0x40 /* Set address of EPLC read, write register. */ #define RdAddr 0xC0 #define HNib 0x10 enum page0_regs { /* The first six registers hold the ethernet physical station address. */ IDR0 = 0, IDR1 = 1, IDR2 = 2, IDR3 = 3, IDR4 = 4, IDR5 = 5, TBCR0 = 6, TBCR1 = 7, /* The transmit byte count. */ TSR = 8, RSR = 9, /* Tx and Rx status. */ ISR = 10, IMR = 11, /* Interrupt status and mask. */ CMR1 = 12, /* Command register 1. */ CMR2 = 13, /* Command register 2. */ MAR = 14, /* Memory address register. */ ISR_h = 0x1a, IMR_h = 0x1b, CMR1_h = 0x1c, CMR2_h = 0x1d, }; enum page1_regs { PCMR = 6, PDR = 7 }; #define PCMR TBCR0 #define PCMR_h (TBCR0 | 0x10) #define ISR_TxOK 0x01 #define ISR_RxOK 0x04 #define ISR_TxErr 0x02 #define ISRh_RxErr 0x11 /* ISR, high nibble */ #define CMR1h_RESET 0x04 /* Reset. */ #define CMR1h_RxENABLE 0x02 /* Rx unit enable. */ #define CMR1h_TxENABLE 0x01 /* Tx unit enable. */ #define CMR1_ReXmit 0x08 /* Trigger a retransmit. */ #define CMR1_Xmit 0x04 /* Trigger a transmit. */ #define CMR1_IRQ 0x02 /* Interrupt active. */ #define CMR1_BufEnb 0x01 /* Enable the buffer(?). */ #define CMR1_NextPkt 0x01 /* Enable the buffer(?). */ #define CMR2_NULL 8 #define CMR2_IRQOUT 9 #define CMR2_RAMTEST 10 #define CMR2_PAGE 12 /* Set to page 1, for reading the EEPROM. */ #define CMR2h_OFF 0 /* No accept mode. */ #define CMR2h_Physical 1 /* Accept a physical address match only. */ #define CMR2h_Normal 2 /* Accept physical and broadcast address. */ #define CMR2h_PROMISC 3 /* Promiscuous mode. */ extern inline unsigned int read_nibble(short port, unsigned char offset) { outb(EOC+offset, port + DATA); outb(RdAddr+offset, port + DATA); inb(port + STATUS); /* Settling time delay */ return inb(port + STATUS); } extern inline unsigned int read_byteA1(short ioaddr, unsigned char offset) { unsigned char result; outb(Ctrl_LNibRead, ioaddr + CONTROL); inb(ioaddr + STATUS); result = inb(ioaddr + STATUS); outb(Ctrl_HNibRead, ioaddr + CONTROL); result = (result >> 3) & 0x0f; inb(ioaddr + STATUS); /* Settling time delay -- needed! */ inb(ioaddr + STATUS); /* Settling time delay -- needed! */ result |= (inb(ioaddr + STATUS) << 1) & 0xf0; return result; } /* The same as read_byteA1(), but double-reads for stability. */ extern inline unsigned int read_byteA2(short ioaddr, unsigned char offset) { unsigned char result; outb(Ctrl_LNibRead, ioaddr + CONTROL); inb(ioaddr + STATUS); result = inb(ioaddr + STATUS); outb(Ctrl_HNibRead, ioaddr + CONTROL); result = (result >> 3) & 0x0f; inb(ioaddr + STATUS); /* Settling time delay -- needed! */ result |= (inb(ioaddr + STATUS) << 1) & 0xf0; return result; } extern inline void write_nibble(short port, unsigned char reg, unsigned char value) { unsigned char outval; outb(EOC | reg, port + DATA); outval = WrAddr | reg; outb(outval, port + DATA); outb(outval, port + DATA); /* Double write for PS/2. */ outval &= 0xf0; outval |= value; outb(outval, port + DATA); outval &= 0x1f; outb(outval, port + DATA); outb(outval, port + DATA); outb(EOC | outval, port + DATA); } /* Write a byte out using nibble mode. The low nibble is written first. */ extern inline void write_byte(short port, unsigned char offset, unsigned char value) { unsigned char outval; outb(EOC | offset, port + DATA); /* Reset the address register. */ outval = WrAddr | offset; outb(outval, port + DATA); outb(outval, port + DATA); /* Double write for PS/2. */ outb((outval & 0xf0) | (value & 0x0f), port + DATA); outb(value & 0x0f, port + DATA); value >>= 4; outb(value, port + DATA); outb(0x10 | value, port + DATA); outb(0x10 | value, port + DATA); outb(EOC | value, port + DATA); /* Reset the address register. */ } /* Write VALUE to DRAM via LptData * Used for remote DMA write in data mode 0, 2 & 4. */ extern inline void write_byte_to_DRAM(short ioaddr, unsigned char value) { outb(value & 0x0f, ioaddr + DATA); outb((value>>4) | 0x10, ioaddr + DATA); } /* Write VALUE to DRAM via LptCtrl in data mode 1, 3 & 5. */ extern inline void write_byte_to_DRAMA(short ioaddr, unsigned char value) { outb(value & 0x0f, ioaddr + DATA); outb(Ctrl_LNibWrite, ioaddr + CONTROL); outb((value>>4) | 0x10, ioaddr + DATA); outb(Ctrl_HNibWrite, ioaddr + CONTROL); } /* Write word VALUE to DRAM via LptData * Used for remote DMA write in data mode 0, 2 & 4. */ extern inline void write_word_to_DRAM(short ioaddr, unsigned short value) { outb(value & 0x0f, ioaddr + DATA); value >>= 4; outb((value & 0x0f) | 0x10, ioaddr + DATA); value >>= 4; outb(value & 0x0f, ioaddr + DATA); value >>= 4; outb((value & 0x0f) | 0x10, ioaddr + DATA); } extern inline void read_end(short port, unsigned char offset) { outb(EOC+offset, port + DATA); } /* EEPROM_Ctrl bits. */ #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ #define EE_CS 0x02 /* EEPROM chip select. */ #define EE_CLK_HIGH 0x12 #define EE_CLK_LOW 0x16 #define EE_DATA_WRITE 0x01 /* EEPROM chip data in. */ #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ /* Delay between EEPROM clock transitions. */ #define slowly eeprom_delay #define eeprom_delay(ticks) \ do { int _i = 40; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0) /* The EEPROM commands include the alway-set leading bit. */ #define EE_WRITE_CMD (5 << 6) #define EE_READ_CMD (6 << 6) #define EE_ERASE_CMD (7 << 6) #define EE_CMD_SIZE 10 /* The command+address size. */