From phk Fri Aug 19 12:29:36 1994
Subject: Re: The 16550 patch
To: bde@kralizec.zeta.org.au (Bruce Evans)
Date: Fri, 19 Aug 1994 12:29:36 -0700 (PDT)
In-Reply-To: <199408081502.BAA10986@kralizec.zeta.org.au> from "Bruce Evans" at Aug 9, 94 01:02:09 am
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Bruce, did you get a OK back on this one ?


> Some one out there have Pual Richards or who ever came up with the
> final fix for the broken SMC FIFO UARTS chip patch to sio?

> Please send me and John a copy.  Last time I went hunting the mail archive
> for it I could not find it :-(.

I just wrote this version but don't have a buggy chip to test it on.  It
is far from the final fix.

Bruce

*** src/sysc/i386/isa/sio.c	Thu Jun 16 18:08:26 1994
--- src/sys/i386/isa/sio.c	Mon Aug  8 13:54:33 1994
***************
*** 756,765 ****
  		iobase = com->iobase;
  		if (com->hasfifo) {
! 			/* Drain fifo. */
! 			outb(iobase + com_fifo,
! 			     FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST
! 			     | com->ftl);
! 			DELAY(100);
  		}
  		disable_intr();
  		(void) inb(com->line_status_port);
--- 754,781 ----
  		iobase = com->iobase;
  		if (com->hasfifo) {
! 			/*
! 			 * (Re)enable and drain fifos.
! 			 *
! 			 * Certain SMC chips cause problems if the fifos
! 			 * are enabled while input is ready.  Turn off the
! 			 * fifo if necessary to clear the input.  We test
! 			 * the input ready bit after enabling the fifos
! 			 * since we've already enabled them in comparam()
! 			 * and to handle races between enabling and fresh
! 			 * input.
! 			 */
! 			while (TRUE) {
! 				outb(iobase + com_fifo,
! 				     FIFO_RCV_RST | FIFO_XMT_RST
! 				     | FIFO_ENABLE | com->ftl);
! 				DELAY(100);
! 				if (!(inb(com->line_status_port) & LSR_RXRDY))
! 					break;
! 				outb(iobase + com_fifo, 0);
! 				DELAY(100);
! 				(void) inb(com->data_port);
! 			}
  		}
+ 
  		disable_intr();
  		(void) inb(com->line_status_port);



-- 
Poul-Henning Kamp <phk@login.dkuug.dk>
TRW Financial Systems, Inc.
FreeBSD has, until now, not one single time had an undetected error. :-)