; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2022-2024 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================

; REQUIRES: regkeys
; RUN: igc_opt -igc-InsertBranchOpt -regkey EnableAtomicBranch=3 -S %s | FileCheck %s


define i32 @atomicUmax(i32 %mem, i32 %val) {
; CHECK-LABEL: @atomicUmax(
; CHECK-NEXT:    [[ADDBEFORE:%.*]] = add i32 [[MEM:%.*]], 10
; CHECK-NEXT:    [[SOMEUNKOWN:%.*]] = add i32 [[VAL:%.*]], 10
; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x float> @llvm.genx.GenISA.ldptr.v4f32.p131073v4f32.p131073v4f32(i32 [[MEM]], i32 0, i32 0, i32 0, <4 x float> addrspace(131073)* undef, <4 x float> addrspace(131073)* null, i32 0, i32 0, i32 0)
; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i64 0
; CHECK-NEXT:    [[TMP3:%.*]] = bitcast float [[TMP2]] to i32
; CHECK-NEXT:    [[TMP4:%.*]] = icmp ugt i32 [[SOMEUNKOWN]], [[TMP3]]
; CHECK-NEXT:    br i1 [[TMP4]], label [[ATOMIC_IF_TRUE:%.*]], label [[ATOMIC_IF_END:%.*]]
; CHECK:       atomic.if.true:
; CHECK-NEXT:    [[ATOMIC:%.*]] = call i32 @llvm.genx.GenISA.intatomicraw.i32.p131073v4f32(<4 x float> addrspace(131073)* null, i32 [[MEM]], i32 [[SOMEUNKOWN]], i32 13)
; CHECK-NEXT:    br label [[ATOMIC_IF_END]]
; CHECK:       atomic.if.end:
; CHECK-NEXT:    [[TMP5:%.*]] = phi i32 [ [[ATOMIC]], [[ATOMIC_IF_TRUE]] ], [ [[TMP3]], [[TMP0:%.*]] ]
; CHECK-NEXT:    [[ADDAFTER:%.*]] = add i32 [[TMP5]], 15
; CHECK-NEXT:    ret i32 [[ADDAFTER]]
;
  %addBefore = add i32 %mem, 10
  %someUnkown = add i32 %val, 10
  %atomic = call i32 @llvm.genx.GenISA.intatomicraw.i32.p131073v4f32(<4 x float> addrspace(131073)* null, i32 %mem, i32 %someUnkown, i32 13)
  %addAfter = add i32 %atomic, 15
  ret i32 %addAfter
}

define i32 @atomicIadd0Raw(i32 %mem, i32 %val) {
; CHECK-LABEL: @atomicIadd0Raw(
; CHECK-NEXT:    [[ADDBEFORE:%.*]] = add i32 [[MEM:%.*]], 10
; CHECK-NEXT:    [[SOMEUNKNOWN:%.*]] = add i32 [[VAL:%.*]], 10
; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[SOMEUNKNOWN]], 0
; CHECK-NEXT:    br i1 [[TMP1]], label [[ATOMIC_IF_TRUE:%.*]], label [[ATOMIC_IF_FALSE:%.*]]
; CHECK:       atomic.if.true:
; CHECK-NEXT:    [[ATOMIC:%.*]] = call i32 @llvm.genx.GenISA.intatomicraw.i32.p131073v4f32(<4 x float> addrspace(131073)* null, i32 [[MEM]], i32 [[SOMEUNKNOWN]], i32 0)
; CHECK-NEXT:    br label [[ATOMIC_IF_END:%.*]]
; CHECK:       atomic.if.false:
; CHECK-NEXT:    [[TMP2:%.*]] = call <4 x float> @llvm.genx.GenISA.ldptr.v4f32.p131073v4f32.p131073v4f32(i32 [[MEM]], i32 0, i32 0, i32 0, <4 x float> addrspace(131073)* undef, <4 x float> addrspace(131073)* null, i32 0, i32 0, i32 0)
; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i64 0
; CHECK-NEXT:    [[TMP4:%.*]] = bitcast float [[TMP3]] to i32
; CHECK-NEXT:    br label [[ATOMIC_IF_END]]
; CHECK:       atomic.if.end:
; CHECK-NEXT:    [[TMP5:%.*]] = phi i32 [ [[ATOMIC]], [[ATOMIC_IF_TRUE]] ], [ [[TMP4]], [[ATOMIC_IF_FALSE]] ]
; CHECK-NEXT:    [[ADDAFTER:%.*]] = add i32 [[TMP5]], 15
; CHECK-NEXT:    ret i32 [[ADDAFTER]]
;
  %addBefore = add i32 %mem, 10
  %someUnknown = add i32 %val, 10
  %atomic = call i32 @llvm.genx.GenISA.intatomicraw.i32.p131073v4f32(<4 x float> addrspace(131073)* null, i32 %mem, i32 %someUnknown, i32 0)
  %addAfter = add i32 %atomic, 15
  ret i32 %addAfter
}

; Function Desc:
; Output:
; Arg 0: Dst Buffer
; Arg 1: dst address
; Arg 2: src0
; Arg 3: Instruction type (add, or, xor etc)
; Function Attrs: argmemonly nounwind
declare i32 @llvm.genx.GenISA.intatomicraw.i32.p131073v4f32(<4 x float> addrspace(131073)*, i32, i32, i32) #0

attributes #0 = { argmemonly nounwind }

