patch-2.1.102 linux/arch/i386/kernel/smp.c
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- Lines: 86
- Date:
Thu May 14 09:43:35 1998
- Orig file:
v2.1.101/linux/arch/i386/kernel/smp.c
- Orig date:
Thu May 7 22:51:46 1998
diff -u --recursive --new-file v2.1.101/linux/arch/i386/kernel/smp.c linux/arch/i386/kernel/smp.c
@@ -636,9 +636,16 @@
value = apic_read(APIC_SPIV);
value |= (1<<8); /* Enable APIC (bit==1) */
value &= ~(1<<9); /* Enable focus processor (bit==0) */
+ value |= 0xff; /* Set spurious IRQ vector to 0xff */
apic_write(APIC_SPIV,value);
+ value = apic_read(APIC_TASKPRI);
+ value &= ~APIC_TPRI_MASK; /* Set Task Priority to 'accept all' */
+ apic_write(APIC_TASKPRI,value);
+
udelay(100); /* B safe */
+ ack_APIC_irq();
+ udelay(100);
}
__initfunc(void smp_callin(void))
@@ -1152,12 +1159,6 @@
__restore_flags(flags);
}
-void funny (void)
-{
- send_IPI(APIC_DEST_ALLBUT,0x30 /*IO_APIC_VECTOR(11)*/);
- for(;;)__cli();
-}
-
/*
* A non wait message cannot pass data or cpu source info. This current setup
* is only safe because the kernel lock owner is the only person who can send
@@ -1474,19 +1475,18 @@
}
/*
- * Reschedule call back
+ * Reschedule call back (not used currently)
*/
+
asmlinkage void smp_reschedule_interrupt(void)
{
int cpu = smp_processor_id();
ack_APIC_irq();
- for (;;) __cli();
/*
* This looks silly, but we actually do need to wait
* for the global interrupt lock.
*/
- printk("huh, this is used, where???\n");
irq_enter(cpu, 0);
need_resched = 1;
irq_exit(cpu, 0);
@@ -1522,6 +1522,15 @@
}
/*
+ * This interrupt should _never_ happen with our APIC/SMP architecture
+ */
+asmlinkage void smp_spurious_interrupt(void)
+{
+ ack_APIC_irq ();
+ printk("spurious APIC interrupt, ayiee, should never happen.\n");
+}
+
+/*
* This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
* per second. We assume that the caller has already set up the local
* APIC.
@@ -1564,7 +1573,7 @@
* APIC double write bug.
*/
-#define APIC_DIVISOR 1
+#define APIC_DIVISOR 16
void setup_APIC_timer (unsigned int clocks)
{
@@ -1588,7 +1597,7 @@
*/
tmp_value = apic_read(APIC_TDCR);
apic_write(APIC_TDCR , (tmp_value & ~APIC_TDR_DIV_1 )
- | APIC_TDR_DIV_1);
+ | APIC_TDR_DIV_16);
tmp_value = apic_read(APIC_TMICT);
apic_write(APIC_TMICT, clocks/APIC_DIVISOR);
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