patch-2.1.97 linux/arch/sparc64/kernel/dtlb_prot.S

• Lines: 46
• Date: Tue Apr 14 17:44:20 1998
• Orig file: v2.1.96/linux/arch/sparc64/kernel/dtlb_prot.S
• Orig date: Sat Aug 16 09:51:08 1997

diff -u --recursive --new-file v2.1.96/linux/arch/sparc64/kernel/dtlb_prot.S linux/arch/sparc64/kernel/dtlb_prot.S
@@ -1,9 +1,9 @@
-/* $Id: dtlb_prot.S,v 1.14 1997/08/03 09:07:00 davem Exp $
+/* $Id: dtlb_prot.S,v 1.15 1998/01/14 17:14:46 jj Exp $
  * dtlb_prot.S:	Data TLB protection code, this is included directly
  *              into the trap table.
  *
  * Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  */
 
 	/* We know kernel never takes protection trap,
@@ -15,12 +15,12 @@
 
 				/* ICACHE line 1 */
   /*0x00*/	ldxa		[%g0] ASI_DMMU, %g1		! Get TAG_TARGET
-  /*0x04*/	srlx		%g1, 8, %g3			! Position PGD offset
-  /*0x08*/	sllx		%g1, 2, %g4			! Position PMD offset
-  /*0x0c*/	and		%g3, %g2, %g3			! Mask PGD offset
-  /*0x10*/	and		%g4, %g2, %g4			! Mask PMD offset
-  /*0x14*/	ldxa		[%g7 + %g3] ASI_PHYS_USE_EC, %g5	! Load PGD
-  /*0x18*/	ldxa		[%g5 + %g4] ASI_PHYS_USE_EC, %g4	! Load PMD
+  /*0x04*/	srlx		%g1, 10, %g3			! Position PGD offset
+  /*0x08*/	and		%g1, 0xffe, %g4			! Mask PMD offset
+  /*0x0c*/	and		%g3, 0xffc, %g3			! Mask PGD offset
+  /*0x10*/	add		%g4, %g4, %g4			! Position PMD offset
+  /*0x14*/	lduwa		[%g7 + %g3] ASI_PHYS_USE_EC, %g5	! Load PGD
+  /*0x18*/	lduwa		[%g5 + %g4] ASI_PHYS_USE_EC, %g4	! Load PMD
   /*0x1c*/	ldxa		[%g0] ASI_DMMU_TSB_8KB_PTR, %g1		! For PTE offset
 
 				/* ICACHE line 2 */
@@ -34,10 +34,10 @@
   /*0x3c*/	ldxa		[%g5] ASI_DMMU, %g4			! From MMU
 
 				/* ICACHE line 3 */
-  /*0x40*/	add		%g2, 7, %g5				! Compute mask
-  /*0x44*/	andn		%g4, %g5, %g4				! Mask page
-  /*0x48*/	mov		TLB_SFSR, %g5				! read SFSR
-  /*0x4c*/	ldxa		[%g5] ASI_DMMU, %g5			! from DMMU for
+  /*0x40*/	mov		TLB_SFSR, %g5				! read SFSR
+  /*0x44*/	srlx		%g4, 13, %g4				!   Prepare...
+  /*0x48*/	ldxa		[%g5] ASI_DMMU, %g5			! from DMMU for
+  /*0x4c*/	sllx		%g4, 13, %g4				!   ...and mask page
   /*0x50*/	and		%g5, 0x10, %g5				! context bit
   /*0x54*/	or		%g4, %g5, %g4				! for prot trap
 1:/*0x58*/	stxa		%g0, [%g4] ASI_DMMU_DEMAP		! TLB flush page