patch-2.2.8 linux/include/asm-ppc/softirq.h

• Lines: 71
• Date: Thu Apr 29 12:39:07 1999
• Orig file: v2.2.7/linux/include/asm-ppc/softirq.h
• Orig date: Tue Mar 23 14:35:48 1999

diff -u --recursive --new-file v2.2.7/linux/include/asm-ppc/softirq.h linux/include/asm-ppc/softirq.h
@@ -4,7 +4,7 @@
 #include <asm/atomic.h>
 #include <asm/hardirq.h>
 
-extern unsigned int local_bh_count[NR_CPUS];
+extern unsigned int ppc_local_bh_count[NR_CPUS];
 
 #define get_active_bhs()	(bh_mask & bh_active)
 #define clear_active_bhs(x)	atomic_clear_mask((x),&bh_active)
@@ -29,6 +29,7 @@
 }
 
 #ifdef __SMP__
+
 /*
  * The locking mechanism for base handlers, to prevent re-entrancy,
  * is entirely private to an implementation, it should not be
@@ -55,7 +56,7 @@
 {
 	if (!test_and_set_bit(0,&global_bh_count)) {
 		if (atomic_read(&global_bh_lock) == 0) {
-			++local_bh_count[cpu];
+			++ppc_local_bh_count[cpu];
 			return 1;
 		}
 		clear_bit(0,&global_bh_count);
@@ -65,30 +66,30 @@
 
 static inline void softirq_endlock(int cpu)
 {
-	local_bh_count[cpu]--;
+	ppc_local_bh_count[cpu]--;
 	clear_bit(0,&global_bh_count);
 }
 
-#else /* __SMP__ */
+#else
 
 extern inline void start_bh_atomic(void)
 {
-	local_bh_count[smp_processor_id()]++;
+	ppc_local_bh_count[smp_processor_id()]++;
 	barrier();
 }
 
 extern inline void end_bh_atomic(void)
 {
 	barrier();
-	local_bh_count[smp_processor_id()]--;
+	ppc_local_bh_count[smp_processor_id()]--;
 }
 
 /* These are for the irq's testing the lock */
-#define softirq_trylock(cpu)	(local_bh_count[cpu] ? 0 : (local_bh_count[cpu]=1))
-#define softirq_endlock(cpu)	(local_bh_count[cpu] = 0)
-#define synchronize_bh()	do { } while (0)
+#define softirq_trylock(cpu)	(ppc_local_bh_count[cpu] ? 0 : (ppc_local_bh_count[cpu]=1))
+#define softirq_endlock(cpu)	(ppc_local_bh_count[cpu] = 0)
+#define synchronize_bh()	barrier()
 
-#endif /* __SMP__ */
+#endif	/* SMP */
 
 /*
  * These use a mask count to correctly handle
@@ -107,4 +108,4 @@
 		bh_mask |= 1 << nr;
 }
 
-#endif
+#endif	/* __ASM_SOFTIRQ_H */