patch-2.4.12 linux/arch/sparc64/kernel/dtlb_backend.S

• Lines: 59
• Date: Wed Oct 10 23:42:46 2001
• Orig file: v2.4.11/linux/arch/sparc64/kernel/dtlb_backend.S
• Orig date: Tue Oct 9 17:06:51 2001

diff -u --recursive --new-file v2.4.11/linux/arch/sparc64/kernel/dtlb_backend.S linux/arch/sparc64/kernel/dtlb_backend.S
@@ -1,4 +1,4 @@
-/* $Id: dtlb_backend.S,v 1.15 2001/09/24 21:54:09 davem Exp $
+/* $Id: dtlb_backend.S,v 1.16 2001/10/09 04:02:11 davem Exp $
  * dtlb_backend.S: Back end to DTLB miss replacement strategy.
  *                 This is included directly into the trap table.
  *
@@ -41,23 +41,25 @@
 	ldxa		[%g1 + %g1] ASI_DMMU, %g4	! Get TAG_ACCESS
 	add		%g3, %g3, %g5			! Compute VPTE base
 	cmp		%g4, %g5			! VPTE miss?
-	blu,pn		%xcc, from_tl1_trap		! Fall to tl0 miss
+	bgeu,pt		%xcc, 1f			! Continue here
 	 andcc		%g4, TAG_CONTEXT_BITS, %g5	! From Nucleus? (for tl0 miss)
-	sllx		%g6, VPTE_SHIFT, %g4		! Position TAG_ACCESS
-	or		%g4, %g5, %g4			! Prepare TAG_ACCESS
-	mov		TSB_REG, %g1			! Grab TSB reg
+	ba,pt		%xcc, from_tl1_trap		! Fall to tl0 miss
+	 rdpr		%tl, %g5			! For tl0 miss TL==3 test
+1:	sllx		%g6, VPTE_SHIFT, %g4		! Position TAG_ACCESS
 
 /* TLB1 ** ICACHE line 2: Quick VPTE miss	  	*/
+	or		%g4, %g5, %g4			! Prepare TAG_ACCESS
+	mov		TSB_REG, %g1			! Grab TSB reg
 	ldxa		[%g1] ASI_DMMU, %g5		! Doing PGD caching?
 	srlx		%g6, (TLB_PMD_SHIFT - 1), %g1	! Position PMD offset
 	be,pn		%xcc, sparc64_vpte_nucleus	! Is it from Nucleus?
 	 and		%g1, TLB_PMD_MASK, %g1		! Mask PMD offset bits
 	brnz,pt		%g5, sparc64_vpte_continue	! Yep, go like smoke
 	 add		%g1, %g1, %g1			! Position PMD offset some more
-	srlx		%g6, (TLB_PGD_SHIFT - 2), %g5	! Position PGD offset
-	and		%g5, TLB_PGD_MASK, %g5		! Mask PGD offset
 
 /* TLB1 ** ICACHE line 3: Quick VPTE miss	  	*/
+	srlx		%g6, (TLB_PGD_SHIFT - 2), %g5	! Position PGD offset
+	and		%g5, TLB_PGD_MASK, %g5		! Mask PGD offset
 	lduwa		[%g7 + %g5] ASI_PHYS_USE_EC, %g5! Load PGD
 	brz,pn		%g5, vpte_noent			! Valid?
 sparc64_kpte_continue:
@@ -66,18 +68,16 @@
 	lduwa		[%g5 + %g1] ASI_PHYS_USE_EC, %g5! Load PMD
 	sllx		%g5, 11, %g5			! Shift into place
 	brz,pn		%g5, vpte_noent			! Valid?
+
+/* TLB1 ** ICACHE line 4: Quick VPTE miss	  	*/
 	 FILL_VALID_SZ_BITS1(%g1)			! Put _PAGE_VALID into %g1
 	FILL_VALID_SZ_BITS2(%g1)			! Put _PAGE_VALID into %g1
 	or		%g5, VPTE_BITS, %g5		! Prepare VPTE data
-
-/* TLB1 ** ICACHE line 4: Quick VPTE miss	  	*/
 	or		%g5, %g1, %g5			! ...
 	mov		TLB_SFSR, %g1			! Restore %g1 value
 	stxa		%g5, [%g0] ASI_DTLB_DATA_IN	! Load VPTE into TLB
 	stxa		%g4, [%g1 + %g1] ASI_DMMU	! Restore previous TAG_ACCESS
 	retry						! Load PTE once again
-	nop
-	nop
 	FILL_VALID_SZ_BITS_NOP
 
 #undef VPTE_SHIFT