patch-2.4.20 linux-2.4.20/arch/mips/au1000/common/irq.c
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- Lines: 435
- Date:
Thu Nov 28 15:53:09 2002
- Orig file:
linux-2.4.19/arch/mips/au1000/common/irq.c
- Orig date:
Fri Aug 2 17:39:43 2002
diff -urN linux-2.4.19/arch/mips/au1000/common/irq.c linux-2.4.20/arch/mips/au1000/common/irq.c
@@ -51,6 +51,8 @@
#include <asm/pb1000.h>
#elif defined(CONFIG_MIPS_PB1500)
#include <asm/pb1500.h>
+#elif defined(CONFIG_MIPS_PB1100)
+#include <asm/pb1100.h>
#else
#error unsupported alchemy board
#endif
@@ -103,86 +105,86 @@
if (irq_nr > AU1000_LAST_INTC0_INT) {
switch (type) {
case INTC_INT_RISE_EDGE: /* 0:0:1 */
- outl(1<<(irq_nr-32), IC1_CFG2CLR);
- outl(1<<(irq_nr-32), IC1_CFG1CLR);
- outl(1<<(irq_nr-32), IC1_CFG0SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG0SET);
break;
case INTC_INT_FALL_EDGE: /* 0:1:0 */
- outl(1<<(irq_nr-32), IC1_CFG2CLR);
- outl(1<<(irq_nr-32), IC1_CFG1SET);
- outl(1<<(irq_nr-32), IC1_CFG0CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
break;
case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
- outl(1<<(irq_nr-32), IC1_CFG2SET);
- outl(1<<(irq_nr-32), IC1_CFG1CLR);
- outl(1<<(irq_nr-32), IC1_CFG0SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG2SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG0SET);
break;
case INTC_INT_LOW_LEVEL: /* 1:1:0 */
- outl(1<<(irq_nr-32), IC1_CFG2SET);
- outl(1<<(irq_nr-32), IC1_CFG1SET);
- outl(1<<(irq_nr-32), IC1_CFG0CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG2SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG1SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
break;
case INTC_INT_DISABLED: /* 0:0:0 */
- outl(1<<(irq_nr-32), IC1_CFG0CLR);
- outl(1<<(irq_nr-32), IC1_CFG1CLR);
- outl(1<<(irq_nr-32), IC1_CFG2CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
break;
default: /* disable the interrupt */
printk("unexpected int type %d (irq %d)\n", type, irq_nr);
- outl(1<<(irq_nr-32), IC1_CFG0CLR);
- outl(1<<(irq_nr-32), IC1_CFG1CLR);
- outl(1<<(irq_nr-32), IC1_CFG2CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
return;
}
if (int_req) /* assign to interrupt request 1 */
- outl(1<<(irq_nr-32), IC1_ASSIGNCLR);
+ au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
else /* assign to interrupt request 0 */
- outl(1<<(irq_nr-32), IC1_ASSIGNSET);
- outl(1<<(irq_nr-32), IC1_SRCSET);
- outl(1<<(irq_nr-32), IC1_MASKCLR);
- outl(1<<(irq_nr-32), IC1_WAKECLR);
+ au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
+ au_writel(1<<(irq_nr-32), IC1_SRCSET);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
+ au_writel(1<<(irq_nr-32), IC1_WAKECLR);
}
else {
switch (type) {
case INTC_INT_RISE_EDGE: /* 0:0:1 */
- outl(1<<irq_nr, IC0_CFG2CLR);
- outl(1<<irq_nr, IC0_CFG1CLR);
- outl(1<<irq_nr, IC0_CFG0SET);
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG0SET);
break;
case INTC_INT_FALL_EDGE: /* 0:1:0 */
- outl(1<<irq_nr, IC0_CFG2CLR);
- outl(1<<irq_nr, IC0_CFG1SET);
- outl(1<<irq_nr, IC0_CFG0CLR);
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
+ au_writel(1<<irq_nr, IC0_CFG1SET);
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
break;
case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
- outl(1<<irq_nr, IC0_CFG2SET);
- outl(1<<irq_nr, IC0_CFG1CLR);
- outl(1<<irq_nr, IC0_CFG0SET);
+ au_writel(1<<irq_nr, IC0_CFG2SET);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG0SET);
break;
case INTC_INT_LOW_LEVEL: /* 1:1:0 */
- outl(1<<irq_nr, IC0_CFG2SET);
- outl(1<<irq_nr, IC0_CFG1SET);
- outl(1<<irq_nr, IC0_CFG0CLR);
+ au_writel(1<<irq_nr, IC0_CFG2SET);
+ au_writel(1<<irq_nr, IC0_CFG1SET);
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
break;
case INTC_INT_DISABLED: /* 0:0:0 */
- outl(1<<irq_nr, IC0_CFG0CLR);
- outl(1<<irq_nr, IC0_CFG1CLR);
- outl(1<<irq_nr, IC0_CFG2CLR);
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
break;
default: /* disable the interrupt */
printk("unexpected int type %d (irq %d)\n", type, irq_nr);
- outl(1<<irq_nr, IC0_CFG0CLR);
- outl(1<<irq_nr, IC0_CFG1CLR);
- outl(1<<irq_nr, IC0_CFG2CLR);
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
return;
}
if (int_req) /* assign to interrupt request 1 */
- outl(1<<irq_nr, IC0_ASSIGNCLR);
+ au_writel(1<<irq_nr, IC0_ASSIGNCLR);
else /* assign to interrupt request 0 */
- outl(1<<irq_nr, IC0_ASSIGNSET);
- outl(1<<irq_nr, IC0_SRCSET);
- outl(1<<irq_nr, IC0_MASKCLR);
- outl(1<<irq_nr, IC0_WAKECLR);
+ au_writel(1<<irq_nr, IC0_ASSIGNSET);
+ au_writel(1<<irq_nr, IC0_SRCSET);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
+ au_writel(1<<irq_nr, IC0_WAKECLR);
}
au_sync();
}
@@ -191,7 +193,7 @@
static unsigned int startup_irq(unsigned int irq_nr)
{
local_enable_irq(irq_nr);
- return 0;
+ return 0;
}
@@ -205,12 +207,12 @@
inline void local_enable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), IC1_MASKSET);
- outl(1<<(irq_nr-32), IC1_WAKESET);
+ au_writel(1<<(irq_nr-32), IC1_MASKSET);
+ au_writel(1<<(irq_nr-32), IC1_WAKESET);
}
else {
- outl(1<<irq_nr, IC0_MASKSET);
- outl(1<<irq_nr, IC0_WAKESET);
+ au_writel(1<<irq_nr, IC0_MASKSET);
+ au_writel(1<<irq_nr, IC0_WAKESET);
}
au_sync();
}
@@ -219,12 +221,12 @@
inline void local_disable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), IC1_MASKCLR);
- outl(1<<(irq_nr-32), IC1_WAKECLR);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
+ au_writel(1<<(irq_nr-32), IC1_WAKECLR);
}
else {
- outl(1<<irq_nr, IC0_MASKCLR);
- outl(1<<irq_nr, IC0_WAKECLR);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
+ au_writel(1<<irq_nr, IC0_WAKECLR);
}
au_sync();
}
@@ -233,12 +235,12 @@
static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), IC1_RISINGCLR);
- outl(1<<(irq_nr-32), IC1_MASKCLR);
+ au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
}
else {
- outl(1<<irq_nr, IC0_RISINGCLR);
- outl(1<<irq_nr, IC0_MASKCLR);
+ au_writel(1<<irq_nr, IC0_RISINGCLR);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
}
au_sync();
}
@@ -247,12 +249,12 @@
static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), IC1_FALLINGCLR);
- outl(1<<(irq_nr-32), IC1_MASKCLR);
+ au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
}
else {
- outl(1<<irq_nr, IC0_FALLINGCLR);
- outl(1<<irq_nr, IC0_MASKCLR);
+ au_writel(1<<irq_nr, IC0_FALLINGCLR);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
}
au_sync();
}
@@ -265,7 +267,7 @@
au_sync();
#if defined(CONFIG_MIPS_PB1000)
if (irq_nr == AU1000_GPIO_15) {
- writew(0x8000, PB1000_MDR); /* ack int */
+ au_writel(0x8000, PB1000_MDR); /* ack int */
au_sync();
}
#endif
@@ -279,12 +281,12 @@
local_enable_irq(irq_nr);
}
else {
- printk("warning: end_irq %d did not enable (%x)\n",
+ printk("warning: end_irq %d did not enable (%x)\n",
irq_nr, irq_desc[irq_nr].status);
}
#if defined(CONFIG_MIPS_PB1000)
if (irq_nr == AU1000_GPIO_15) {
- writew(0x4000, PB1000_MDR); /* enable int */
+ au_writel(0x4000, PB1000_MDR); /* enable int */
au_sync();
}
#endif
@@ -297,13 +299,13 @@
save_and_cli(flags);
if (controller) {
- mask = readl(IC1_MASKSET);
+ mask = au_readl(IC1_MASKSET);
for (i=32; i<64; i++) {
local_disable_irq(i);
}
}
else {
- mask = readl(IC0_MASKSET);
+ mask = au_readl(IC0_MASKSET);
for (i=0; i<32; i++) {
local_disable_irq(i);
}
@@ -327,9 +329,9 @@
}
}
if (controller)
- new_mask = readl(IC1_MASKSET);
+ new_mask = au_readl(IC1_MASKSET);
else
- new_mask = readl(IC0_MASKSET);
+ new_mask = au_readl(IC0_MASKSET);
restore_flags(flags);
}
@@ -390,10 +392,6 @@
init_generic_irq();
- /* override the generic vec0 handler */
- memcpy((void *)KSEG0, &except_vec0_au1000, 0x80);
- flush_icache_range(KSEG0, KSEG0 + 0x200);
-
for (i = 0; i <= AU1000_MAX_INTR; i++) {
switch (i) {
case AU1000_UART0_INT:
@@ -406,6 +404,12 @@
case AU1000_SSI1_INT:
#endif
+#ifdef CONFIG_MIPS_PB1100
+ case AU1000_UART1_INT:
+
+ case AU1000_SSI0_INT:
+ case AU1000_SSI1_INT:
+#endif
case AU1000_DMA_INT_BASE:
case AU1000_DMA_INT_BASE+1:
case AU1000_DMA_INT_BASE+2:
@@ -419,9 +423,14 @@
case AU1000_IRDA_RX_INT:
case AU1000_MAC0_DMA_INT:
+#ifdef CONFIG_MIPS_PB1000
case AU1000_MAC1_DMA_INT:
-
+#endif
+#ifdef CONFIG_MIPS_PB1500
+ case AU1000_MAC1_DMA_INT:
+#endif
case AU1500_GPIO_204:
+
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
@@ -441,16 +450,24 @@
case AU1500_GPIO_205:
case AU1500_GPIO_207:
#endif
+
+#ifdef CONFIG_MIPS_PB1100
+ case AU1000_GPIO_9: // PCMCIA Card Fully_Interted#
+ case AU1000_GPIO_10: // PCMCIA_STSCHG#
+ case AU1000_GPIO_11: // PCMCIA_IRQ#
+ case AU1000_GPIO_13: // DC_IRQ#
+ case AU1000_GPIO_23: // 2-wire SCL
+#endif
setup_local_irq(i, INTC_INT_LOW_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
case AU1000_ACSYNC_INT:
case AU1000_AC97C_INT:
- case AU1000_USB_DEV_REQ_INT:
- case AU1000_USB_DEV_SUS_INT:
case AU1000_TOY_INT:
case AU1000_TOY_MATCH0_INT:
case AU1000_TOY_MATCH1_INT:
+ case AU1000_USB_DEV_SUS_INT:
+ case AU1000_USB_DEV_REQ_INT:
case AU1000_RTC_INT:
case AU1000_RTC_MATCH0_INT:
case AU1000_RTC_MATCH1_INT:
@@ -478,7 +495,7 @@
/* If local serial I/O used for debug port, enter kgdb at once */
puts("Waiting for kgdb to connect...");
set_debug_traps();
- breakpoint();
+ breakpoint();
#endif
}
@@ -494,10 +511,21 @@
int irq = 0, i;
static unsigned long intc0_req0 = 0;
- intc0_req0 |= inl(IC0_REQ0INT);
+ intc0_req0 |= au_readl(IC0_REQ0INT);
if (!intc0_req0) return;
+ /*
+ * Because of the tight timing of SETUP token to reply
+ * transactions, the USB devices-side packet complete
+ * interrupt needs the highest priority.
+ */
+ if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
+ intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
+ do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
+ return;
+ }
+
for (i=0; i<32; i++) {
if ((intc0_req0 & (1<<i))) {
intc0_req0 &= ~(1<<i);
@@ -514,7 +542,7 @@
int irq = 0, i;
static unsigned long intc0_req1 = 0;
- intc0_req1 = inl(IC0_REQ1INT);
+ intc0_req1 = au_readl(IC0_REQ1INT);
if (!intc0_req1) return;
@@ -527,7 +555,7 @@
counter0_irq(irq, NULL, regs);
local_enable_irq(irq);
}
- else
+ else
#endif
{
do_IRQ(irq, regs);
@@ -550,20 +578,20 @@
volatile unsigned short levels, mdr;
unsigned char ide_status;
- intc1_req0 |= inl(IC1_REQ0INT);
+ intc1_req0 |= au_readl(IC1_REQ0INT);
if (!intc1_req0) return;
-#ifdef CONFIG_MIPS_PB1000
- writew(1, CPLD_AUX0); /* debug led 0 */
+#if defined(CONFIG_MIPS_PB1000) && defined(DEBUG_IRQ)
+ au_writel(1, CPLD_AUX0); /* debug led 0 */
#endif
for (i=0; i<32; i++) {
if ((intc1_req0 & (1<<i))) {
intc1_req0 &= ~(1<<i);
-#ifdef CONFIG_MIPS_PB1000
- writew(2, CPLD_AUX0); /* turn on debug led 1 */
+#if defined(CONFIG_MIPS_PB1000) && defined(DEBUG_IRQ)
+ au_writel(2, CPLD_AUX0); /* turn on debug led 1 */
do_IRQ(irq+32, regs);
- writew(0, CPLD_AUX0); /* turn off debug led 1 */
+ au_writel(0, CPLD_AUX0); /* turn off debug led 1 */
#else
do_IRQ(irq+32, regs);
#endif
@@ -571,8 +599,8 @@
}
irq++;
}
-#ifdef CONFIG_MIPS_PB1000
- writew(0, CPLD_AUX0);
+#if defined(CONFIG_MIPS_PB1000) && defined(DEBUG_IRQ)
+ au_writel(0, CPLD_AUX0);
#endif
}
@@ -582,7 +610,7 @@
int irq = 0, i;
static unsigned long intc1_req1 = 0;
- intc1_req1 |= inl(IC1_REQ1INT);
+ intc1_req1 |= au_readl(IC1_REQ1INT);
if (!intc1_req1) return;
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TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)