patch-2.4.20 linux-2.4.20/arch/mips/au1000/pb1000/setup.c
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- Lines: 275
- Date:
Thu Nov 28 15:53:09 2002
- Orig file:
linux-2.4.19/arch/mips/au1000/pb1000/setup.c
- Orig date:
Fri Aug 2 17:39:43 2002
diff -urN linux-2.4.19/arch/mips/au1000/pb1000/setup.c linux-2.4.20/arch/mips/au1000/pb1000/setup.c
@@ -67,7 +67,6 @@
extern struct ide_ops *ide_ops;
#endif
-void (*__wbflush) (void);
extern struct rtc_ops no_rtc_ops;
extern char * __init prom_getcmdline(void);
extern void au1000_restart(char *);
@@ -76,11 +75,7 @@
extern struct resource ioport_resource;
extern struct resource iomem_resource;
-
-void au1000_wbflush(void)
-{
- __asm__ volatile ("sync");
-}
+void __init bus_error_init(void) { /* nothing */ }
void __init au1000_setup(void)
{
@@ -88,7 +83,7 @@
u32 pin_func, static_cfg0;
u32 sys_freqctrl, sys_clksrc;
u32 prid = read_32bit_cp0_register(CP0_PRID);
-
+
argptr = prom_getcmdline();
/* Various early Au1000 Errata corrected by this */
@@ -99,15 +94,14 @@
argptr = prom_getcmdline();
strcat(argptr, " console=ttyS0,115200");
}
-#endif
+#endif
rtc_ops = &no_rtc_ops;
- __wbflush = au1000_wbflush;
_machine_restart = au1000_restart;
_machine_halt = au1000_halt;
_machine_power_off = au1000_power_off;
- // IO/MEM resources.
+ // IO/MEM resources.
set_io_port_base(0);
ioport_resource.start = 0x10000000;
ioport_resource.end = 0xffffffff;
@@ -121,8 +115,8 @@
#endif
// set AUX clock to 12MHz * 8 = 96 MHz
- outl(8, SYS_AUXPLL);
- outl(0, SYS_PINSTATERD);
+ au_writel(8, SYS_AUXPLL);
+ au_writel(0, SYS_PINSTATERD);
udelay(100);
#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
@@ -138,19 +132,19 @@
#endif
/* zero and disable FREQ2 */
- sys_freqctrl = inl(SYS_FREQCTRL0);
+ sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
- outl(sys_freqctrl, SYS_FREQCTRL0);
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
/* zero and disable USBH/USBD clocks */
- sys_clksrc = inl(SYS_CLKSRC);
+ sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
- outl(sys_clksrc, SYS_CLKSRC);
+ au_writel(sys_clksrc, SYS_CLKSRC);
- sys_freqctrl = inl(SYS_FREQCTRL0);
+ sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
- sys_clksrc = inl(SYS_CLKSRC);
+ sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
switch (prid & 0x000000FF)
@@ -159,17 +153,17 @@
case 0x01: /* HA */
case 0x02: /* HB */
/* CPU core freq to 48MHz to slow it way down... */
- outl(4, SYS_CPUPLL);
+ au_writel(4, SYS_CPUPLL);
/*
* Setup 48MHz FREQ2 from CPUPLL for USB Host
*/
/* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
- outl(sys_freqctrl, SYS_FREQCTRL0);
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
/* CPU core freq to 384MHz */
- outl(0x20, SYS_CPUPLL);
+ au_writel(0x20, SYS_CPUPLL);
printk("Au1000: 48MHz OHCI workaround enabled\n");
break;
@@ -177,7 +171,7 @@
default: /* HC and newer */
// FREQ2 = aux/2 = 48 MHz
sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
- outl(sys_freqctrl, SYS_FREQCTRL0);
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
break;
}
@@ -190,64 +184,69 @@
#ifdef CONFIG_AU1000_USB_DEVICE
sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
#endif
- outl(sys_clksrc, SYS_CLKSRC);
+ au_writel(sys_clksrc, SYS_CLKSRC);
#ifdef CONFIG_USB_OHCI
// enable host controller and wait for reset done
- outl(0x08, USB_HOST_CONFIG);
+ au_writel(0x08, USB_HOST_CONFIG);
udelay(1000);
- outl(0x0E, USB_HOST_CONFIG);
+ au_writel(0x0E, USB_HOST_CONFIG);
udelay(1000);
- inl(USB_HOST_CONFIG); // throw away first read
- while (!(inl(USB_HOST_CONFIG) & 0x10))
- inl(USB_HOST_CONFIG);
+ au_readl(USB_HOST_CONFIG); // throw away first read
+ while (!(au_readl(USB_HOST_CONFIG) & 0x10))
+ au_readl(USB_HOST_CONFIG);
#endif
-
+
// configure pins GPIO[14:9] as GPIO
- pin_func = inl(SYS_PINFUNC) & (u32)(~0x8080);
+ pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
#ifndef CONFIG_AU1000_USB_DEVICE
// 2nd USB port is USB host
pin_func |= 0x8000;
#endif
- outl(pin_func, SYS_PINFUNC);
- outl(0x2800, SYS_TRIOUTCLR);
- outl(0x0030, SYS_OUTPUTCLR);
+ au_writel(pin_func, SYS_PINFUNC);
+ au_writel(0x2800, SYS_TRIOUTCLR);
+ au_writel(0x0030, SYS_OUTPUTCLR);
#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
- // make gpio 15 an input (for interrupt line)
- pin_func = inl(SYS_PINFUNC) & (u32)(~0x100);
- // we don't need I2S, so make it available for GPIO[31:29]
+ // make gpio 15 an input (for interrupt line)
+ pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100);
+ // we don't need I2S, so make it available for GPIO[31:29]
pin_func |= (1<<5);
- outl(pin_func, SYS_PINFUNC);
+ au_writel(pin_func, SYS_PINFUNC);
+
+ au_writel(0x8000, SYS_TRIOUTCLR);
- outl(0x8000, SYS_TRIOUTCLR);
-
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
- static_cfg0 = inl(MEM_STCFG0) & (u32)(~0xc00);
- outl(static_cfg0, MEM_STCFG0);
+ static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00);
+ au_writel(static_cfg0, MEM_STCFG0);
// configure RCE2* for LCD
- outl(0x00000004, MEM_STCFG2);
+ au_writel(0x00000004, MEM_STCFG2);
// MEM_STTIME2
- outl(0x09000000, MEM_STTIME2);
+ au_writel(0x09000000, MEM_STTIME2);
// Set 32-bit base address decoding for RCE2*
- outl(0x10003ff0, MEM_STADDR2);
+ au_writel(0x10003ff0, MEM_STADDR2);
// PCI CPLD setup
// expand CE0 to cover PCI
- outl(0x11803e40, MEM_STADDR1);
+ au_writel(0x11803e40, MEM_STADDR1);
+
+ // burst visibility on
+ au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
- // burst visibility on
- outl(inl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
+ au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing
+ au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA
- outl(0x83, MEM_STCFG1); // ewait enabled, flash timing
- outl(0x33030a10, MEM_STTIME1); // slower timing for FPGA
+ /* setup the static bus controller */
+ au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
+ au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
+ au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
#ifdef CONFIG_FB_E1356
if ((argptr = strstr(argptr, "video=")) == NULL) {
@@ -258,39 +257,35 @@
#ifdef CONFIG_PCI
- outl(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
- outl(0, SDRAM_MBAR); // set mbar to 0
- outl(0x2, SDRAM_CMD); // enable memory accesses
+ au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
+ au_writel(0, SDRAM_MBAR); // set mbar to 0
+ au_writel(0x2, SDRAM_CMD); // enable memory accesses
au_sync_delay(1);
#endif
#ifndef CONFIG_SERIAL_NONSTANDARD
/* don't touch the default serial console */
- outl(0, UART0_ADDR + UART_CLK);
+ au_writel(0, UART0_ADDR + UART_CLK);
#endif
- outl(0, UART1_ADDR + UART_CLK);
- outl(0, UART2_ADDR + UART_CLK);
- outl(0, UART3_ADDR + UART_CLK);
+ au_writel(0, UART1_ADDR + UART_CLK);
+ au_writel(0, UART2_ADDR + UART_CLK);
+ au_writel(0, UART3_ADDR + UART_CLK);
#ifdef CONFIG_BLK_DEV_IDE
- {
- argptr = prom_getcmdline();
- strcat(argptr, " ide0=noprobe");
- }
ide_ops = &std_ide_ops;
#endif
// setup irda clocks
// aux clock, divide by 2, clock from 2/4 divider
- writel(readl(SYS_CLKSRC) | 0x7, SYS_CLKSRC);
- pin_func = inl(SYS_PINFUNC) & (u32)(~(1<<2)); // clear IRTXD
- outl(pin_func, SYS_PINFUNC);
+ au_writel(au_readl(SYS_CLKSRC) | 0x7, SYS_CLKSRC);
+ pin_func = au_readl(SYS_PINFUNC) & (u32)(~(1<<2)); // clear IRTXD
+ au_writel(pin_func, SYS_PINFUNC);
- while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
- outl(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
+ au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
au_sync();
- while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
- outl(0, SYS_TOYTRIM);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
+ au_writel(0, SYS_TOYTRIM);
/* Enable Au1000 BCLK switching - note: sed1356 must not use
* its BCLK (Au1000 LCLK) for any timings */
@@ -301,7 +296,7 @@
case 0x02: /* HB */
break;
default: /* HC and newer */
- outl(0x00000060, 0xb190003c);
+ au_writel(0x00000060, 0xb190003c);
break;
}
}
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