patch-2.4.20 linux-2.4.20/arch/mips/galileo-boards/ev64120/pci_bios.c
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- Lines: 76
- Date:
Thu Nov 28 15:53:10 2002
- Orig file:
linux-2.4.19/arch/mips/galileo-boards/ev64120/pci_bios.c
- Orig date:
Fri Aug 2 17:39:43 2002
diff -urN linux-2.4.19/arch/mips/galileo-boards/ev64120/pci_bios.c linux-2.4.20/arch/mips/galileo-boards/ev64120/pci_bios.c
@@ -441,7 +441,7 @@
* pci_range_ck -
*
* Check if the pci device that are trying to access does really exists
- * on the evaluation board.
+ * on the evaluation board.
*
* Inputs :
* bus - bus number (0 for PCI 0 ; 1 for PCI 1)
@@ -455,18 +455,18 @@
//DBG(KERN_INFO "p_r_c %d %d\n",bus,dev);
if (((bus == 0) || (bus == 1)) && (dev >= 6) && (dev <= 8))
return 0; // Bus/Device Number OK
- return -1; // Bus/Device Number not OK
+ return -1; // Bus/Device Number not OK
}
/*
* pciXReadConfigReg - Read from a PCI configuration register
- * - Make sure the GT is configured as a master before
+ * - Make sure the GT is configured as a master before
* reading from another device on the PCI.
* - The function takes care of Big/Little endian conversion.
* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
* spec)
- * pciDevNum: The device number needs to be addressed.
- * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+ * pciDevNum: The device number needs to be addressed.
+ * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
* cause register to make sure the data is valid
*
* Configuration Address 0xCF8:
@@ -518,7 +518,7 @@
to stabilize, so the READ can work.
*/
if (PCI_SLOT(device->devfn) == SELF) { /* This board */
- /* when configurating our own PCI 1 L-unit the access is through
+ /* when configurating our own PCI 1 L-unit the access is through
the PCI 0 interface with reg number = reg number + 0x80 */
DataForRegCf8 |= 0x80;
GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
@@ -538,13 +538,13 @@
/*
* pciXWriteConfigReg - Write to a PCI configuration register
- * - Make sure the GT is configured as a master before
+ * - Make sure the GT is configured as a master before
* writingto another device on the PCI.
* - The function takes care of Big/Little endian conversion.
* Inputs: unsigned int regOffset: The register offset as it apears in the
- * GT spec
+ * GT spec
* (or any other PCI device spec)
- * pciDevNum: The device number needs to be addressed.
+ * pciDevNum: The device number needs to be addressed.
*
* Configuration Address 0xCF8:
*
@@ -584,7 +584,7 @@
to stabilize, so the WRITE can work.
*/
if (PCI_SLOT(device->devfn) == SELF) { /* This board */
- /* when configurating our own PCI 1 L-unit the access is through
+ /* when configurating our own PCI 1 L-unit the access is through
the PCI 0 interface with reg number = reg number + 0x80 */
DataForRegCf8 |= 0x80;
GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
@@ -906,7 +906,7 @@
}
void pcibios_align_resource(void *data, struct resource *res,
- unsigned long size)
+ unsigned long size, unsigned long align)
{
struct pci_dev *dev = data;
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TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)