patch-2.4.20 linux-2.4.20/arch/mips/kernel/setup.c
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- Lines: 587
- Date:
Thu Nov 28 15:53:10 2002
- Orig file:
linux-2.4.19/arch/mips/kernel/setup.c
- Orig date:
Fri Aug 2 17:39:43 2002
diff -urN linux-2.4.19/arch/mips/kernel/setup.c linux-2.4.20/arch/mips/kernel/setup.c
@@ -44,22 +44,15 @@
#endif
/*
- * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
- * the implementation of the "wait" feature differs between CPU families. This
- * points to the function that implements CPU specific wait.
- * The wait instruction stops the pipeline and reduces the power consumption of
- * the CPU very much.
- */
-void (*cpu_wait)(void) = NULL;
-
-/*
* There are several bus types available for MIPS machines. "RISC PC"
* type machines have ISA, EISA, VLB or PCI available, DECstations
* have Turbochannel or Q-Bus, SGI has GIO, there are lots of VME
* boxes ...
* This flag is set if a EISA slots are available.
*/
+#ifdef CONFIG_EISA
int EISA_bus = 0;
+#endif
struct screen_info screen_info;
@@ -122,403 +115,9 @@
static struct resource code_resource = { "Kernel code" };
static struct resource data_resource = { "Kernel data" };
-static inline void check_wait(void)
-{
- printk("Checking for 'wait' instruction... ");
- switch(mips_cpu.cputype) {
- case CPU_R3081:
- case CPU_R3081E:
- cpu_wait = r3081_wait;
- printk(" available.\n");
- break;
- case CPU_TX3927:
- case CPU_TX39XX:
- cpu_wait = r39xx_wait;
- printk(" available.\n");
- break;
- case CPU_R4200:
-/* case CPU_R4300: */
- case CPU_R4600:
- case CPU_R4640:
- case CPU_R4650:
- case CPU_R4700:
- case CPU_R5000:
- case CPU_NEVADA:
- case CPU_RM7000:
- case CPU_TX49XX:
- case CPU_4KC:
- case CPU_4KEC:
- case CPU_4KSC:
- case CPU_5KC:
-/* case CPU_20KC:*/
- cpu_wait = r4k_wait;
- printk(" available.\n");
- break;
- default:
- printk(" unavailable.\n");
- break;
- }
-}
-
-void __init check_bugs(void)
-{
- check_wait();
-}
-
-/*
- * Probe whether cpu has config register by trying to play with
- * alternate cache bit and see whether it matters.
- * It's used by cpu_probe to distinguish between R3000A and R3081.
- */
-static inline int cpu_has_confreg(void)
-{
-#ifdef CONFIG_CPU_R3000
- extern unsigned long r3k_cache_size(unsigned long);
- unsigned long size1, size2;
- unsigned long cfg = read_32bit_cp0_register(CP0_CONF);
-
- size1 = r3k_cache_size(ST0_ISC);
- write_32bit_cp0_register(CP0_CONF, cfg^CONF_AC);
- size2 = r3k_cache_size(ST0_ISC);
- write_32bit_cp0_register(CP0_CONF, cfg);
- return size1 != size2;
-#else
- return 0;
-#endif
-}
-
-/*
- * Get the FPU Implementation/Revision.
- */
-static inline unsigned long cpu_get_fpu_id(void)
-{
- unsigned long tmp, fpu_id;
-
- tmp = read_32bit_cp0_register(CP0_STATUS);
- __enable_fpu();
- fpu_id = read_32bit_cp1_register(CP1_REVISION);
- write_32bit_cp0_register(CP0_STATUS, tmp);
- return fpu_id;
-}
-
-/*
- * Check the CPU has an FPU the official way.
- */
-static inline int cpu_has_fpu(void)
-{
- return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
-}
-
-/* declaration of the global struct */
-struct mips_cpu mips_cpu = {
- processor_id: PRID_IMP_UNKNOWN,
- fpu_id: FPIR_IMP_NONE,
- cputype: CPU_UNKNOWN
-};
-
-/* Shortcut for assembler access to mips_cpu.options */
-int *cpuoptions = &mips_cpu.options;
-
-#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
- | MIPS_CPU_COUNTER | MIPS_CPU_CACHE_CDEX)
-
-static inline void cpu_probe(void)
-{
-#ifdef CONFIG_CPU_MIPS32
- unsigned long config0 = read_32bit_cp0_register(CP0_CONFIG);
- unsigned long config1;
-
- if (config0 & (1 << 31)) {
- /* MIPS32 compliant CPU. Read Config 1 register. */
- mips_cpu.isa_level = MIPS_CPU_ISA_M32;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC;
- config1 = read_mips32_cp0_config1();
- if (config1 & (1 << 3))
- mips_cpu.options |= MIPS_CPU_WATCH;
- if (config1 & (1 << 2))
- mips_cpu.options |= MIPS_CPU_MIPS16;
- if (config1 & (1 << 1))
- mips_cpu.options |= MIPS_CPU_EJTAG;
- if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU;
- mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
- }
-#endif
- mips_cpu.processor_id = read_32bit_cp0_register(CP0_PRID);
- switch (mips_cpu.processor_id & 0xff0000) {
- case PRID_COMP_LEGACY:
- switch (mips_cpu.processor_id & 0xff00) {
- case PRID_IMP_R2000:
- mips_cpu.cputype = CPU_R2000;
- mips_cpu.isa_level = MIPS_CPU_ISA_I;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
- if (cpu_has_fpu())
- mips_cpu.options |= MIPS_CPU_FPU;
- mips_cpu.tlbsize = 64;
- break;
- case PRID_IMP_R3000:
- if ((mips_cpu.processor_id & 0xff) == PRID_REV_R3000A)
- if (cpu_has_confreg())
- mips_cpu.cputype = CPU_R3081E;
- else
- mips_cpu.cputype = CPU_R3000A;
- else
- mips_cpu.cputype = CPU_R3000;
- mips_cpu.isa_level = MIPS_CPU_ISA_I;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
- if (cpu_has_fpu())
- mips_cpu.options |= MIPS_CPU_FPU;
- mips_cpu.tlbsize = 64;
- break;
- case PRID_IMP_R4000:
- if ((mips_cpu.processor_id & 0xff) == PRID_REV_R4400)
- mips_cpu.cputype = CPU_R4400SC;
- else
- mips_cpu.cputype = CPU_R4000SC;
- mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_WATCH |
- MIPS_CPU_VCE;
- mips_cpu.tlbsize = 48;
- break;
- case PRID_IMP_VR41XX:
- mips_cpu.cputype = CPU_VR41XX;
- mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS;
- mips_cpu.tlbsize = 32;
- break;
- case PRID_IMP_R4300:
- mips_cpu.cputype = CPU_R4300;
- mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR;
- mips_cpu.tlbsize = 32;
- break;
- case PRID_IMP_R4600:
- mips_cpu.cputype = CPU_R4600;
- mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
- mips_cpu.tlbsize = 48;
- break;
- #if 0
- case PRID_IMP_R4650:
- /*
- * This processor doesn't have an MMU, so it's not
- * "real easy" to run Linux on it. It is left purely
- * for documentation. Commented out because it shares
- * it's c0_prid id number with the TX3900.
- */
- mips_cpu.cputype = CPU_R4650;
- mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
- mips_cpu.tlbsize = 48;
- break;
- #endif
- case PRID_IMP_TX39:
- mips_cpu.isa_level = MIPS_CPU_ISA_I;
- mips_cpu.options = MIPS_CPU_TLB;
-
- if ((mips_cpu.processor_id & 0xf0) ==
- (PRID_REV_TX3927 & 0xf0)) {
- mips_cpu.cputype = CPU_TX3927;
- mips_cpu.tlbsize = 64;
- mips_cpu.icache.ways = 2;
- mips_cpu.dcache.ways = 2;
- } else {
- switch (mips_cpu.processor_id & 0xff) {
- case PRID_REV_TX3912:
- mips_cpu.cputype = CPU_TX3912;
- mips_cpu.tlbsize = 32;
- break;
- case PRID_REV_TX3922:
- mips_cpu.cputype = CPU_TX3922;
- mips_cpu.tlbsize = 64;
- break;
- default:
- mips_cpu.cputype = CPU_UNKNOWN;
- break;
- }
- }
- break;
- case PRID_IMP_R4700:
- mips_cpu.cputype = CPU_R4700;
- mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR;
- mips_cpu.tlbsize = 48;
- break;
- case PRID_IMP_TX49:
- mips_cpu.cputype = CPU_TX49XX;
- mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR;
- mips_cpu.tlbsize = 48;
- mips_cpu.icache.ways = 4;
- mips_cpu.dcache.ways = 4;
- break;
- case PRID_IMP_R5000:
- mips_cpu.cputype = CPU_R5000;
- mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR;
- mips_cpu.tlbsize = 48;
- break;
- case PRID_IMP_R5432:
- mips_cpu.cputype = CPU_R5432;
- mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_WATCH;
- mips_cpu.tlbsize = 48;
- break;
- case PRID_IMP_R5500:
- mips_cpu.cputype = CPU_R5500;
- mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_WATCH;
- mips_cpu.tlbsize = 48;
- break;
- case PRID_IMP_NEVADA:
- mips_cpu.cputype = CPU_NEVADA;
- mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
- mips_cpu.tlbsize = 48;
- mips_cpu.icache.ways = 2;
- mips_cpu.dcache.ways = 2;
- break;
- case PRID_IMP_R6000:
- mips_cpu.cputype = CPU_R6000;
- mips_cpu.isa_level = MIPS_CPU_ISA_II;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
- mips_cpu.tlbsize = 32;
- break;
- case PRID_IMP_R6000A:
- mips_cpu.cputype = CPU_R6000A;
- mips_cpu.isa_level = MIPS_CPU_ISA_II;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
- mips_cpu.tlbsize = 32;
- break;
- case PRID_IMP_RM7000:
- mips_cpu.cputype = CPU_RM7000;
- mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR;
- /*
- * Undocumented RM7000: Bit 29 in the info register of
- * the RM7000 v2.0 indicates if the TLB has 48 or 64
- * entries.
- *
- * 29 1 => 64 entry JTLB
- * 0 => 48 entry JTLB
- */
- mips_cpu.tlbsize = (get_info() & (1 << 29)) ? 64 : 48;
- break;
- case PRID_IMP_R8000:
- mips_cpu.cputype = CPU_R8000;
- mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_FPU | MIPS_CPU_32FPR;
- mips_cpu.tlbsize = 384; /* has wierd TLB: 3-way x 128 */
- break;
- case PRID_IMP_R10000:
- mips_cpu.cputype = CPU_R10000;
- mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_FPU | MIPS_CPU_32FPR |
- MIPS_CPU_COUNTER | MIPS_CPU_WATCH;
- mips_cpu.tlbsize = 64;
- break;
- case PRID_IMP_R12000:
- mips_cpu.cputype = CPU_R12000;
- mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_FPU | MIPS_CPU_32FPR |
- MIPS_CPU_COUNTER | MIPS_CPU_WATCH;
- mips_cpu.tlbsize = 64;
- break;
- default:
- mips_cpu.cputype = CPU_UNKNOWN;
- break;
- }
- break;
-#ifdef CONFIG_CPU_MIPS32
- case PRID_COMP_MIPS:
- switch (mips_cpu.processor_id & 0xff00) {
- case PRID_IMP_4KC:
- mips_cpu.cputype = CPU_4KC;
- break;
- case PRID_IMP_4KEC:
- mips_cpu.cputype = CPU_4KEC;
- break;
- case PRID_IMP_4KSC:
- mips_cpu.cputype = CPU_4KSC;
- break;
- case PRID_IMP_5KC:
- mips_cpu.cputype = CPU_5KC;
- mips_cpu.isa_level = MIPS_CPU_ISA_M64;
- break;
- case PRID_IMP_20KC:
- mips_cpu.cputype = CPU_20KC;
- mips_cpu.isa_level = MIPS_CPU_ISA_M64;
- break;
- default:
- mips_cpu.cputype = CPU_UNKNOWN;
- break;
- }
- break;
- case PRID_COMP_ALCHEMY:
- switch (mips_cpu.processor_id & 0xff00) {
- case PRID_IMP_AU1_REV1:
- case PRID_IMP_AU1_REV2:
- if (mips_cpu.processor_id & 0xff000000)
- mips_cpu.cputype = CPU_AU1500;
- else
- mips_cpu.cputype = CPU_AU1000;
- break;
- default:
- mips_cpu.cputype = CPU_UNKNOWN;
- break;
- }
- break;
-#endif /* CONFIG_CPU_MIPS32 */
- case PRID_COMP_SIBYTE:
- switch (mips_cpu.processor_id & 0xff00) {
- case PRID_IMP_SB1:
- mips_cpu.cputype = CPU_SB1;
- mips_cpu.isa_level = MIPS_CPU_ISA_M64;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
- MIPS_CPU_MCHECK;
-#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
- /* FPU in pass1 is known to have issues. */
- mips_cpu.options |= MIPS_CPU_FPU;
-#endif
- break;
- default:
- mips_cpu.cputype = CPU_UNKNOWN;
- break;
- }
- break;
- default:
- mips_cpu.cputype = CPU_UNKNOWN;
- }
- if (mips_cpu.options & MIPS_CPU_FPU)
- mips_cpu.fpu_id = cpu_get_fpu_id();
-}
-
-static inline void cpu_report(void)
-{
- printk("CPU revision is: %08x\n", mips_cpu.processor_id);
- if (mips_cpu.options & MIPS_CPU_FPU)
- printk("FPU revision is: %08x\n", mips_cpu.fpu_id);
-}
-
asmlinkage void __init
init_arch(int argc, char **argv, char **envp, int *prom_vec)
{
- unsigned int s;
-
/* Determine which MIPS variant we are running on. */
cpu_probe();
@@ -650,10 +249,14 @@
void ip22_setup(void);
void ev96100_setup(void);
void malta_setup(void);
+ void sead_setup(void);
void ikos_setup(void);
void momenco_ocelot_setup(void);
+ void momenco_ocelot_g_setup(void);
void nino_setup(void);
void nec_osprey_setup(void);
+ void nec_eagle_setup(void);
+ void zao_capcella_setup(void);
void jmr3927_setup(void);
void it8172_setup(void);
void swarm_setup(void);
@@ -679,13 +282,13 @@
#ifdef CONFIG_PC_KEYB
kbd_ops = &no_kbd_ops;
#endif
-
+
rtc_ops = &no_rtc_ops;
switch(mips_machgroup)
{
#ifdef CONFIG_BAGET_MIPS
- case MACH_GROUP_BAGET:
+ case MACH_GROUP_BAGET:
baget_setup();
break;
#endif
@@ -719,6 +322,16 @@
momenco_ocelot_setup();
break;
#endif
+#ifdef CONFIG_MOMENCO_OCELOT_G
+ case MACH_GROUP_MOMENCO:
+ momenco_ocelot_g_setup();
+ break;
+#endif
+#ifdef CONFIG_MIPS_SEAD
+ case MACH_GROUP_UNKNOWN:
+ sead_setup();
+ break;
+#endif
#ifdef CONFIG_SGI_IP22
/* As of now this is only IP22. */
case MACH_GROUP_SGI:
@@ -745,9 +358,25 @@
ddb_setup();
break;
#endif
-#ifdef CONFIG_NEC_OSPREY
+#ifdef CONFIG_CPU_VR41XX
case MACH_GROUP_NEC_VR41XX:
- nec_osprey_setup();
+ switch (mips_machtype) {
+#ifdef CONFIG_NEC_OSPREY
+ case MACH_NEC_OSPREY:
+ nec_osprey_setup();
+ break;
+#endif
+#ifdef CONFIG_NEC_EAGLE
+ case MACH_NEC_EAGLE:
+ nec_eagle_setup();
+ break;
+#endif
+#ifdef CONFIG_ZAO_CAPCELLA
+ case MACH_ZAO_CAPCELLA:
+ zao_capcella_setup();
+ break;
+#endif
+ }
break;
#endif
#ifdef CONFIG_MIPS_EV96100
@@ -765,7 +394,7 @@
case MACH_GROUP_GLOBESPAN:
it8172_setup();
break;
-#endif
+#endif
#ifdef CONFIG_NINO
case MACH_GROUP_PHILIPS:
nino_setup();
@@ -776,6 +405,11 @@
au1000_setup();
break;
#endif
+#ifdef CONFIG_MIPS_PB1100
+ case MACH_GROUP_ALCHEMY:
+ au1100_setup();
+ break;
+#endif
#ifdef CONFIG_MIPS_PB1500
case MACH_GROUP_ALCHEMY:
au1500_setup();
@@ -815,8 +449,8 @@
#define MAXMEM_PFN PFN_DOWN(MAXMEM)
#ifdef CONFIG_BLK_DEV_INITRD
- tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8;
- if (tmp < (unsigned long)&_end)
+ tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8;
+ if (tmp < (unsigned long)&_end)
tmp += PAGE_SIZE;
initrd_header = (unsigned long *)tmp;
if (initrd_header[0] == 0x494E5244) {
@@ -952,17 +586,17 @@
}
initrd_below_start_ok = 1;
if (initrd_start) {
- unsigned long initrd_size = ((unsigned char *)initrd_end) - ((unsigned char *)initrd_start);
+ unsigned long initrd_size = ((unsigned char *)initrd_end) - ((unsigned char *)initrd_start);
printk("Initial ramdisk at: 0x%p (%lu bytes)\n",
- (void *)initrd_start,
+ (void *)initrd_start,
initrd_size);
- if ((void *)initrd_end > phys_to_virt(PFN_PHYS(max_low_pfn))) {
+ if (PHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) {
printk("initrd extends beyond end of memory "
"(0x%lx > 0x%p)\ndisabling initrd\n",
- initrd_end,
- phys_to_virt(PFN_PHYS(max_low_pfn)));
+ PHYSADDR(initrd_end),
+ PFN_PHYS(max_low_pfn));
initrd_start = initrd_end = 0;
- }
+ }
}
#endif /* CONFIG_BLK_DEV_INITRD */
@@ -1013,25 +647,6 @@
}
}
-void r3081_wait(void)
-{
- unsigned long cfg = read_32bit_cp0_register(CP0_CONF);
- write_32bit_cp0_register(CP0_CONF, cfg|CONF_HALT);
-}
-
-void r39xx_wait(void)
-{
- unsigned long cfg = read_32bit_cp0_register(CP0_CONF);
- write_32bit_cp0_register(CP0_CONF, cfg|TX39_CONF_HALT);
-}
-
-void r4k_wait(void)
-{
- __asm__(".set\tmips3\n\t"
- "wait\n\t"
- ".set\tmips0");
-}
-
static int __init fpu_disable(char *s)
{
mips_cpu.options &= ~MIPS_CPU_FPU;
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