patch-2.4.20 linux-2.4.20/arch/mips/mm/c-sb1.c
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- Lines: 144
- Date:
Thu Nov 28 15:53:10 2002
- Orig file:
linux-2.4.19/arch/mips/mm/c-sb1.c
- Orig date:
Fri Aug 2 17:39:43 2002
diff -urN linux-2.4.19/arch/mips/mm/c-sb1.c linux-2.4.20/arch/mips/mm/c-sb1.c
@@ -12,11 +12,11 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
+ *
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
+ */
#include <linux/config.h>
#include <linux/init.h>
#include <asm/mmu_context.h>
@@ -63,7 +63,7 @@
* if we miss in the icache, and have dirty data in the
* L1 dcache, then we'll go out to memory (or the L2) and
* get the not-as-recent data.
- *
+ *
* So the only time we have to flush the dcache is when
* we're flushing the icache. Since the L2 is fully
* coherent to everything, including I/O, we never have
@@ -80,7 +80,7 @@
* Haven't worried too much about speed here; given that we're flushing
* the icache, the time to invalidate is dwarfed by the time it's going
* to take to refill it. Register usage:
- *
+ *
* $1 - moving cache index
* $2 - set count
*/
@@ -104,7 +104,7 @@
".set noreorder \n"
".set mips2 \n"
"sync \n"
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS /* Bug 1384 */
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS /* Bug 1384 */
"sync \n"
#endif
".set pop \n");
@@ -160,7 +160,7 @@
".set noreorder \n"
".set noat \n"
".set mips4 \n"
- " move $1, %0 \n"
+ " move $1, %0 \n"
"1: \n"
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
".align 3 \n"
@@ -199,7 +199,7 @@
".set noreorder \n"
".set noat \n"
".set mips4 \n"
- " move $1, %0 \n"
+ " move $1, %0 \n"
".align 3 \n"
"1: cache %3, (0<<13)($1) \n" /* Index-inval this address */
" cache %3, (1<<13)($1) \n" /* Index-inval this address */
@@ -279,9 +279,9 @@
static inline void protected_writeback_dcache_line(unsigned long addr)
{
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
- /* Have to be sure the TLB entry exists for the cache op,
+ /* Have to be sure the TLB entry exists for the cache op,
so we have to be sure that nothing happens in between the
- lw and the cache op
+ lw and the cache op
*/
unsigned long flags;
local_irq_save(flags);
@@ -371,7 +371,7 @@
* Haven't worried too much about speed here; given that we're flushing
* the icache, the time to invalidate is dwarfed by the time it's going
* to take to refill it. Register usage:
- *
+ *
* $1 - moving cache index
* $2 - set count
*/
@@ -403,23 +403,23 @@
/*
* This only needs to make sure stores done up to this
- * point are visible to other agents outside the CPU. Given
- * the coherent nature of the ZBbus, all that's required here is
+ * point are visible to other agents outside the CPU. Given
+ * the coherent nature of the ZBbus, all that's required here is
* a sync to make sure the data gets out to the caches and is
- * visible to an arbitrary A Phase from an external agent
- *
+ * visible to an arbitrary A Phase from an external agent
+ *
* Actually, I'm not even sure that's necessary; the semantics
* of this function aren't clear. If it's supposed to serve as
- * a memory barrier, this is needed. If it's only meant to
+ * a memory barrier, this is needed. If it's only meant to
* prevent data from being invisible to non-cpu memory accessors
- * for some indefinite period of time (e.g. in a non-coherent
+ * for some indefinite period of time (e.g. in a non-coherent
* dcache) then this function would be a complete nop.
*/
static void sb1_flush_page_to_ram(struct page *page)
{
__asm__ __volatile__(
" sync \n" /* Short pipe */
- :::"memory");
+ :::"memory");
}
/*
@@ -433,13 +433,13 @@
* 6 - 4096
* 7 - Reserved
*/
-
+
static unsigned int decode_cache_sets(unsigned int config_field)
{
if (config_field == 7) {
/* JDCXXX - Find a graceful way to abort. */
return 0;
- }
+ }
return (1<<(config_field + 6));
}
@@ -462,7 +462,7 @@
} else if (config_field == 7) {
/* JDCXXX - Find a graceful way to abort. */
return 0;
- }
+ }
return (1<<(config_field + 1));
}
@@ -519,6 +519,6 @@
_flush_cache_sigtramp = sb1_flush_cache_sigtramp;
_flush_icache_all = sb1_flush_icache_all;
- change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_COW);
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
flush_cache_all();
}
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