patch-2.4.20 linux-2.4.20/include/asm-mips/au1000.h
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- Lines: 314
- Date:
Thu Nov 28 15:53:15 2002
- Orig file:
linux-2.4.19/include/asm-mips/au1000.h
- Orig date:
Fri Aug 2 17:39:45 2002
diff -urN linux-2.4.19/include/asm-mips/au1000.h linux-2.4.20/include/asm-mips/au1000.h
@@ -31,6 +31,7 @@
#ifndef _AU1000_H_
#define _AU1000_H_
+#include <linux/config.h>
#include <linux/delay.h>
#include <asm/io.h>
@@ -52,22 +53,34 @@
mdelay(ms);
}
-void static inline outb_sync(u8 val, int reg)
+void static inline au_writeb(u8 val, int reg)
{
- outb(val, reg);
- au_sync();
+ *(volatile u8 *)(reg) = val;
}
-void static inline outw_sync(u16 val, int reg)
+void static inline au_writew(u16 val, int reg)
{
- outw(val, reg);
- au_sync();
+ *(volatile u16 *)(reg) = val;
}
-void static inline outl_sync(u32 val, int reg)
+void static inline au_writel(u32 val, int reg)
{
- outl(val, reg);
- au_sync();
+ *(volatile u32 *)(reg) = val;
+}
+
+static inline u8 au_readb(unsigned long port)
+{
+ return (*(volatile u8 *)port);
+}
+
+static inline u16 au_readw(unsigned long port)
+{
+ return (*(volatile u16 *)port);
+}
+
+static inline u32 au_readl(unsigned long port)
+{
+ return (*(volatile u32 *)port);
}
/* arch/mips/au1000/common/clocks.c */
@@ -300,6 +313,12 @@
#define AU1000_MAX_INTR 63
+#define AU1100_SD 2
+#define AU1100_GPIO_208_215 29
+// REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE
+
+
+
/* Programmable Counters 0 and 1 */
#define SYS_BASE 0xB1900000
#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
@@ -339,11 +358,36 @@
#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
#define SYS_RTCREAD (SYS_BASE + 0x58)
-
/* I2S Controller */
#define I2S_DATA 0xB1000000
-#define I2S_CONFIG 0xB1000001
-#define I2S_ENABLE 0xB1000002
+ #define I2S_DATA_MASK (0xffffff)
+#define I2S_CONFIG 0xB1000004
+ #define I2S_CONFIG_XU (1<<25)
+ #define I2S_CONFIG_XO (1<<24)
+ #define I2S_CONFIG_RU (1<<23)
+ #define I2S_CONFIG_RO (1<<22)
+ #define I2S_CONFIG_TR (1<<21)
+ #define I2S_CONFIG_TE (1<<20)
+ #define I2S_CONFIG_TF (1<<19)
+ #define I2S_CONFIG_RR (1<<18)
+ #define I2S_CONFIG_RE (1<<17)
+ #define I2S_CONFIG_RF (1<<16)
+ #define I2S_CONFIG_PD (1<<11)
+ #define I2S_CONFIG_LB (1<<10)
+ #define I2S_CONFIG_IC (1<<9)
+ #define I2S_CONFIG_FM_BIT 7
+ #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
+ #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
+ #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
+ #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
+ #define I2S_CONFIG_TN (1<<6)
+ #define I2S_CONFIG_RN (1<<5)
+ #define I2S_CONFIG_SZ_BIT 0
+ #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
+
+#define I2S_CONTROL 0xB1000008
+ #define I2S_CONTROL_D (1<<1)
+ #define I2S_CONTROL_CE (1<<0)
/* USB Host Controller */
// We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address
@@ -398,12 +442,13 @@
#define AU1000_ETH1_BASE 0xB0510000
#define AU1500_ETH0_BASE 0xB1500000
#define AU1500_ETH1_BASE 0xB1510000
+#define AU1100_ETH0_BASE 0xB0500000
/* 4 byte offsets from AU1000_ETH_BASE */
#define MAC_CONTROL 0x0
- #define MAC_RX_ENABLE (1<<2)
+ #define MAC_RX_ENABLE (1<<2)
#define MAC_TX_ENABLE (1<<3)
- #define MAC_DEF_CHECK (1<<5)
+ #define MAC_DEF_CHECK (1<<5)
#define MAC_SET_BL(X) (((X)&0x3)<<6)
#define MAC_AUTO_PAD (1<<8)
#define MAC_DISABLE_RETRY (1<<10)
@@ -428,7 +473,7 @@
#define MAC_MCAST_LOW 0x10
#define MAC_MII_CNTRL 0x14
#define MAC_MII_BUSY (1<<0)
- #define MAC_MII_READ 0
+ #define MAC_MII_READ 0
#define MAC_MII_WRITE (1<<1)
#define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
#define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
@@ -446,6 +491,8 @@
#define AU1000_MAC1_ENABLE 0xB0520004
#define AU1500_MAC0_ENABLE 0xB1520000
#define AU1500_MAC1_ENABLE 0xB1520004
+#define AU1100_MAC0_ENABLE 0xB0520000
+
#define MAC_EN_CLOCK_ENABLE (1<<0)
#define MAC_EN_RESET0 (1<<1)
#define MAC_EN_TOSS (0<<2)
@@ -510,7 +557,7 @@
#define RX_FILTER_FAIL (1<<29)
#define RX_PACKET_FILTER (1<<30)
#define RX_MISSED_FRAME (1<<31)
-
+
#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
@@ -628,12 +675,44 @@
/* SSIO */
#define SSI0_STATUS 0xB1600000
+ #define SSI_STATUS_BF (1<<4)
+ #define SSI_STATUS_OF (1<<3)
+ #define SSI_STATUS_UF (1<<2)
+ #define SSI_STATUS_D (1<<1)
+ #define SSI_STATUS_B (1<<0)
#define SSI0_INT 0xB1600004
+ #define SSI_INT_OI (1<<3)
+ #define SSI_INT_UI (1<<2)
+ #define SSI_INT_DI (1<<1)
#define SSI0_INT_ENABLE 0xB1600008
+ #define SSI_INTE_OIE (1<<3)
+ #define SSI_INTE_UIE (1<<2)
+ #define SSI_INTE_DIE (1<<1)
#define SSI0_CONFIG 0xB1600020
+ #define SSI_CONFIG_AO (1<<24)
+ #define SSI_CONFIG_DO (1<<23)
+ #define SSI_CONFIG_ALEN_BIT 20
+ #define SSI_CONFIG_ALEN_MASK (0x7<<20)
+ #define SSI_CONFIG_DLEN_BIT 16
+ #define SSI_CONFIG_DLEN_MASK (0x7<<16)
+ #define SSI_CONFIG_DD (1<<11)
+ #define SSI_CONFIG_AD (1<<10)
+ #define SSI_CONFIG_BM_BIT 8
+ #define SSI_CONFIG_BM_MASK (0x3<<8)
+ #define SSI_CONFIG_CE (1<<7)
+ #define SSI_CONFIG_DP (1<<6)
+ #define SSI_CONFIG_DL (1<<5)
+ #define SSI_CONFIG_EP (1<<4)
#define SSI0_ADATA 0xB1600024
+ #define SSI_AD_D (1<<24)
+ #define SSI_AD_ADDR_BIT 16
+ #define SSI_AD_ADDR_MASK (0xff<<16)
+ #define SSI_AD_DATA_BIT 0
+ #define SSI_AD_DATA_MASK (0xfff<<0)
#define SSI0_CLKDIV 0xB1600028
#define SSI0_CONTROL 0xB1600100
+ #define SSI_CONTROL_CD (1<<1)
+ #define SSI_CONTROL_E (1<<0)
/* SSI1 */
#define SSI1_STATUS 0xB1680000
@@ -685,12 +764,29 @@
/* GPIO */
#define SYS_PINFUNC 0xB190002C
+ #define SYS_PF_USB (1<<15) /* 2nd USB device/host */
+ #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
+ #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
+ #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
+ #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
+ #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
+ #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
+ #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
+ #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
+ #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
+ #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
+ #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
+ #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
+ #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
+ #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
+ #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
#define SYS_TRIOUTRD 0xB1900100
#define SYS_TRIOUTCLR 0xB1900100
#define SYS_OUTPUTRD 0xB1900108
#define SYS_OUTPUTSET 0xB1900108
#define SYS_OUTPUTCLR 0xB190010C
#define SYS_PINSTATERD 0xB1900110
+#define SYS_PININPUTEN 0xB1900110
/* GPIO2, Au1500 only */
#define GPIO2_BASE 0xB1700000
@@ -712,8 +808,64 @@
/* Clock Controller */
#define SYS_FREQCTRL0 0xB1900020
+ #define SYS_FC_FRDIV2_BIT 22
+ #define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT)
+ #define SYS_FC_FE2 (1<<21)
+ #define SYS_FC_FS2 (1<<20)
+ #define SYS_FC_FRDIV1_BIT 12
+ #define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT)
+ #define SYS_FC_FE1 (1<<11)
+ #define SYS_FC_FS1 (1<<10)
+ #define SYS_FC_FRDIV0_BIT 2
+ #define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT)
+ #define SYS_FC_FE0 (1<<1)
+ #define SYS_FC_FS0 (1<<0)
#define SYS_FREQCTRL1 0xB1900024
+ #define SYS_FC_FRDIV5_BIT 22
+ #define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT)
+ #define SYS_FC_FE5 (1<<21)
+ #define SYS_FC_FS5 (1<<20)
+ #define SYS_FC_FRDIV4_BIT 12
+ #define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT)
+ #define SYS_FC_FE4 (1<<11)
+ #define SYS_FC_FS4 (1<<10)
+ #define SYS_FC_FRDIV3_BIT 2
+ #define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT)
+ #define SYS_FC_FE3 (1<<1)
+ #define SYS_FC_FS3 (1<<0)
#define SYS_CLKSRC 0xB1900028
+ #define SYS_CS_ME1_BIT 27
+ #define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT)
+ #define SYS_CS_DE1 (1<<26)
+ #define SYS_CS_CE1 (1<<25)
+ #define SYS_CS_ME0_BIT 22
+ #define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT)
+ #define SYS_CS_DE0 (1<<21)
+ #define SYS_CS_CE0 (1<<20)
+ #define SYS_CS_MI2_BIT 17
+ #define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT)
+ #define SYS_CS_DI2 (1<<16)
+ #define SYS_CS_CI2 (1<<15)
+ #define SYS_CS_MUH_BIT 12
+ #define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT)
+ #define SYS_CS_DUH (1<<11)
+ #define SYS_CS_CUH (1<<10)
+ #define SYS_CS_MUD_BIT 7
+ #define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT)
+ #define SYS_CS_DUD (1<<6)
+ #define SYS_CS_CUD (1<<5)
+ #define SYS_CS_MIR_BIT 2
+ #define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT)
+ #define SYS_CS_DIR (1<<1)
+ #define SYS_CS_CIR (1<<0)
+
+ #define SYS_CS_MUX_AUX 0x1
+ #define SYS_CS_MUX_FQ0 0x2
+ #define SYS_CS_MUX_FQ1 0x3
+ #define SYS_CS_MUX_FQ2 0x4
+ #define SYS_CS_MUX_FQ3 0x5
+ #define SYS_CS_MUX_FQ4 0x6
+ #define SYS_CS_MUX_FQ5 0x7
#define SYS_CPUPLL 0xB1900060
#define SYS_AUXPLL 0xB1900064
@@ -768,11 +920,19 @@
#define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr
- /* these are all pseudo physical addresses */
-#define Au1500_EXT_CFG 0x20000000
-#define Au1500_PCI_IO_START 0x70000000
-#define Au1500_PCI_IO_END 0x700FFFFF
-#define Au1500_PCI_MEM_START 0x80000000
-#define Au1500_PCI_MEM_END 0x83FFFFFF
+/* All of our structures, like pci resource, have 32 bit members.
+ * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
+ * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
+ * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
+ * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
+ * addresses. For PCI IO, it's simpler because we get to do the ioremap
+ * ourselves and then adjust the device's resources.
+ */
+#define Au1500_EXT_CFG 0x600000000
+#define Au1500_EXT_CFG_TYPE1 0x680000000
+#define Au1500_PCI_IO_START 0x500000000
+#define Au1500_PCI_IO_END 0x5000FFFFF
+#define Au1500_PCI_MEM_START 0x440000000
+#define Au1500_PCI_MEM_END 0x443FFFFFF
#endif
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TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)