patch-2.4.22 linux-2.4.22/arch/mips64/mm/loadmmu.c
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- Lines: 149
- Date:
2003-08-25 04:44:40.000000000 -0700
- Orig file:
linux-2.4.21/arch/mips64/mm/loadmmu.c
- Orig date:
2002-11-28 15:53:10.000000000 -0800
diff -urN linux-2.4.21/arch/mips64/mm/loadmmu.c linux-2.4.22/arch/mips64/mm/loadmmu.c
@@ -4,20 +4,23 @@
* for more details.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 1997, 1999 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1997, 1999, 2000, 2001, 2002, 2003 Ralf Baechle (ralf@gnu.org)
* Copyright (C) 1999 Silicon Graphics, Inc.
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
+#include <linux/module.h>
+#include <asm/bootinfo.h>
+#include <asm/cpu.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
-#include <asm/bootinfo.h>
-#include <asm/cpu.h>
/* memory functions */
void (*_clear_page)(void * page);
@@ -28,62 +31,79 @@
void (*___flush_cache_all)(void);
void (*_flush_cache_mm)(struct mm_struct *mm);
void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
- unsigned long end);
+ unsigned long end);
void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page);
-void (*_flush_cache_sigtramp)(unsigned long addr);
void (*_flush_icache_range)(unsigned long start, unsigned long end);
void (*_flush_icache_page)(struct vm_area_struct *vma, struct page *page);
-void (*_flush_page_to_ram)(struct page * page);
-void (*_flush_icache_all)(void);
-/* MIPS specific cache operations */
-void (*_flush_cache_l2)(void);
-void (*_flush_cache_l1)(void);
+void (*_flush_cache_sigtramp)(unsigned long addr);
+void (*_flush_data_cache_page)(unsigned long addr);
+void (*_flush_icache_all)(void);
+#ifdef CONFIG_NONCOHERENT_IO
/* DMA cache operations. */
void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
void (*_dma_cache_wback)(unsigned long start, unsigned long size);
void (*_dma_cache_inv)(unsigned long start, unsigned long size);
-/* Miscellaneous. */
-void (*_update_mmu_cache)(struct vm_area_struct * vma,
- unsigned long address, pte_t pte);
+EXPORT_SYMBOL(_dma_cache_wback_inv);
+EXPORT_SYMBOL(_dma_cache_wback);
+EXPORT_SYMBOL(_dma_cache_inv);
+
+#endif /* CONFIG_NONCOHERENT_IO */
+extern void ld_mmu_r23000(void);
extern void ld_mmu_r4xx0(void);
+extern void ld_mmu_tx39(void);
+extern void ld_mmu_r6000(void);
+extern void ld_mmu_tfp(void);
extern void ld_mmu_andes(void);
extern void ld_mmu_sb1(void);
extern void sb1_tlb_init(void);
-extern void ld_mmu_mips64(void);
+extern void r3k_tlb_init(void);
extern void r4k_tlb_init(void);
+extern void sb1_tlb_init(void);
void __init load_mmu(void)
{
- if (mips_cpu.options & MIPS_CPU_4KTLB) {
-#if defined (CONFIG_CPU_R4300) \
- || defined (CONFIG_CPU_R4X00) \
- || defined (CONFIG_CPU_R5000) \
- || defined (CONFIG_CPU_NEVADA)
- printk(KERN_INFO "Loading R4000 MMU routines.\n");
+ if (cpu_has_4ktlb) {
+#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \
+ defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \
+ defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \
+ defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32) || \
+ defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \
+ defined(CONFIG_CPU_RM7000)
ld_mmu_r4xx0();
-#endif
-#if defined(CONFIG_CPU_MIPS64)
- printk(KERN_INFO "Loading MIPS64 MMU routines.\n");
- ld_mmu_mips64();
r4k_tlb_init();
#endif
-
- } else switch(mips_cpu.cputype) {
+ } else switch (current_cpu_data.cputype) {
+#ifdef CONFIG_CPU_R3000
+ case CPU_R2000:
+ case CPU_R3000:
+ case CPU_R3000A:
+ case CPU_R3081E:
+ ld_mmu_r23000();
+ r3k_tlb_init();
+ break;
+#endif
+#ifdef CONFIG_CPU_TX39XX
+ case CPU_TX3912:
+ case CPU_TX3922:
+ case CPU_TX3927:
+ ld_mmu_tx39();
+ r3k_tlb_init();
+ break;
+#endif
#ifdef CONFIG_CPU_R10000
case CPU_R10000:
case CPU_R12000:
- printk(KERN_INFO "Loading R10000 MMU routines.\n");
- ld_mmu_andes();
+ ld_mmu_r4xx0();
+ andes_tlb_init();
break;
#endif
-#if defined CONFIG_CPU_SB1
+#ifdef CONFIG_CPU_SB1
case CPU_SB1:
- printk(KERN_INFO "Loading SB1 MMU routines.\n");
ld_mmu_sb1();
sb1_tlb_init();
break;
@@ -94,13 +114,6 @@
break;
default:
- /* XXX We need an generic routine in the MIPS port
- * XXX to jabber stuff onto the screen on all machines
- * XXX before the console is setup. The ARCS prom
- * XXX routines look good for this, but only the SGI
- * XXX code has a full library for that at this time.
- */
- panic("Yeee, unsupported mmu/cache architecture or "
- "wrong compiletime kernel configuration.");
+ panic("Yeee, unsupported mmu/cache architecture.");
}
}
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