patch-2.4.22 linux-2.4.22/arch/mips/mm/c-tx39.c
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- Lines: 575
- Date:
2003-08-25 04:44:40.000000000 -0700
- Orig file:
linux-2.4.21/arch/mips/mm/c-tx39.c
- Orig date:
2002-11-28 15:53:10.000000000 -0800
diff -urN linux-2.4.21/arch/mips/mm/c-tx39.c linux-2.4.22/arch/mips/mm/c-tx39.c
@@ -25,18 +25,24 @@
/* For R3000 cores with R4000 style caches */
static unsigned long icache_size, dcache_size; /* Size in bytes */
-extern long scache_size;
-
-#define icache_lsize mips_cpu.icache.linesz
-#define dcache_lsize mips_cpu.dcache.linesz
#include <asm/r4kcache.h>
+extern void r3k_clear_page(void * page);
+extern void r3k_copy_page(void * to, void * from);
+
extern int r3k_have_wired_reg; /* in r3k-tlb.c */
-static void tx39h_flush_page_to_ram(struct page * page)
-{
-}
+/* This sequence is required to ensure icache is disabled immediately */
+#define TX39_STOP_STREAMING() \
+__asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ "b 1f\n\t" \
+ "nop\n\t" \
+ "1:\n\t" \
+ ".set pop" \
+ )
/* TX39H-style cache flush routines. */
static void tx39h_flush_icache_all(void)
@@ -46,8 +52,10 @@
unsigned long flags, config;
/* disable icache (set ICE#) */
- __save_and_cli(flags);
- config = read_32bit_cp0_register(CP0_CONF);
+ local_irq_save(flags);
+ config = read_c0_conf();
+ write_c0_conf(config & ~TX39_CONF_ICE);
+ TX39_STOP_STREAMING();
/* invalidate icache */
while (start < end) {
@@ -55,46 +63,103 @@
start += 0x200;
}
- write_32bit_cp0_register(CP0_CONF, config);
- __restore_flags(flags);
+ write_c0_conf(config);
+ local_irq_restore(flags);
}
static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
unsigned long end, a;
+ unsigned long dc_lsize = current_cpu_data.dcache.linesz;
iob();
- a = addr & ~(dcache_lsize - 1);
- end = (addr + size) & ~(dcache_lsize - 1);
+ a = addr & ~(dc_lsize - 1);
+ end = (addr + size - 1) & ~(dc_lsize - 1);
while (1) {
invalidate_dcache_line(a); /* Hit_Invalidate_D */
if (a == end) break;
- a += dcache_lsize;
+ a += dc_lsize;
}
}
/* TX39H2,TX39H3 */
-static inline void tx39_flush_cache_all(void)
+static inline void tx39_blast_dcache_page(unsigned long addr)
+{
+ if (current_cpu_data.cputype != CPU_TX3912)
+ blast_dcache16_page(addr);
+}
+
+static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
+{
+ blast_dcache16_page_indexed(addr);
+}
+
+static inline void tx39_blast_dcache(void)
+{
+ blast_dcache16();
+}
+
+static inline void tx39_blast_icache_page(unsigned long addr)
+{
+ unsigned long flags, config;
+ /* disable icache (set ICE#) */
+ local_irq_save(flags);
+ config = read_c0_conf();
+ write_c0_conf(config & ~TX39_CONF_ICE);
+ TX39_STOP_STREAMING();
+ blast_icache16_page(addr);
+ write_c0_conf(config);
+ local_irq_restore(flags);
+}
+
+static inline void tx39_blast_icache_page_indexed(unsigned long addr)
{
unsigned long flags, config;
+ /* disable icache (set ICE#) */
+ local_irq_save(flags);
+ config = read_c0_conf();
+ write_c0_conf(config & ~TX39_CONF_ICE);
+ TX39_STOP_STREAMING();
+ blast_icache16_page_indexed(addr);
+ write_c0_conf(config);
+ local_irq_restore(flags);
+}
- __save_and_cli(flags);
- blast_dcache16_wayLSB();
+static inline void tx39_blast_icache(void)
+{
+ unsigned long flags, config;
/* disable icache (set ICE#) */
- config = read_32bit_cp0_register(CP0_CONF);
- write_32bit_cp0_register(CP0_CONF, config&~TX39_CONF_ICE);
- blast_icache16_wayLSB();
- write_32bit_cp0_register(CP0_CONF, config);
- __restore_flags(flags);
+ local_irq_save(flags);
+ config = read_c0_conf();
+ write_c0_conf(config & ~TX39_CONF_ICE);
+ TX39_STOP_STREAMING();
+ blast_icache16();
+ write_c0_conf(config);
+ local_irq_restore(flags);
+}
+
+static inline void tx39_flush_cache_all(void)
+{
+ if (!cpu_has_dc_aliases)
+ return;
+
+ tx39_blast_dcache();
+ tx39_blast_icache();
+}
+
+static inline void tx39___flush_cache_all(void)
+{
+ tx39_blast_dcache();
+ tx39_blast_icache();
}
static void tx39_flush_cache_mm(struct mm_struct *mm)
{
- if(mm->context != 0) {
-#ifdef DEBUG_CACHE
- printk("cmm[%d]", (int)mm->context);
-#endif
+ if (!cpu_has_dc_aliases)
+ return;
+
+ if (cpu_context(smp_processor_id(), mm) != 0) {
tx39_flush_cache_all();
}
}
@@ -103,28 +168,20 @@
unsigned long start,
unsigned long end)
{
- if(mm->context != 0) {
- unsigned long flags, config;
+ if (!cpu_has_dc_aliases)
+ return;
-#ifdef DEBUG_CACHE
- printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
-#endif
- __save_and_cli(flags);
- blast_dcache16_wayLSB();
- /* disable icache (set ICE#) */
- config = read_32bit_cp0_register(CP0_CONF);
- write_32bit_cp0_register(CP0_CONF, config&~TX39_CONF_ICE);
- blast_icache16_wayLSB();
- write_32bit_cp0_register(CP0_CONF, config);
- __restore_flags(flags);
+ if (cpu_context(smp_processor_id(), mm) != 0) {
+ tx39_blast_dcache();
+ tx39_blast_icache();
}
}
static void tx39_flush_cache_page(struct vm_area_struct *vma,
unsigned long page)
{
+ int exec = vma->vm_flags & VM_EXEC;
struct mm_struct *mm = vma->vm_mm;
- unsigned long flags;
pgd_t *pgdp;
pmd_t *pmdp;
pte_t *ptep;
@@ -133,13 +190,9 @@
* If ownes no valid ASID yet, cannot possibly have gotten
* this page into the cache.
*/
- if(mm->context == 0)
+ if (cpu_context(smp_processor_id(), mm) == 0)
return;
-#ifdef DEBUG_CACHE
- printk("cpage[%d,%08lx]", (int)mm->context, page);
-#endif
- __save_and_cli(flags);
page &= PAGE_MASK;
pgdp = pgd_offset(mm, page);
pmdp = pmd_offset(pgdp, page);
@@ -149,8 +202,8 @@
* If the page isn't marked valid, the page cannot possibly be
* in the cache.
*/
- if(!(pte_val(*ptep) & _PAGE_PRESENT))
- goto out;
+ if (!(pte_val(*ptep) & _PAGE_PRESENT))
+ return;
/*
* Doing flushes for another ASID than the current one is
@@ -158,51 +211,121 @@
* for every cache flush operation. So we do indexed flushes
* in that case, which doesn't overly flush the cache too much.
*/
- if((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
- blast_dcache16_page(page);
- } else {
- /*
- * Do indexed flush, too much work to get the (possible)
- * tlb refills to work correctly.
- */
- page = (KSEG0 + (page & (dcache_size - 1)));
- blast_dcache16_page_indexed_wayLSB(page);
+ if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
+ if (cpu_has_dc_aliases || exec)
+ tx39_blast_dcache_page(page);
+ if (exec)
+ tx39_blast_icache_page(page);
+
+ return;
}
-out:
- __restore_flags(flags);
+
+ /*
+ * Do indexed flush, too much work to get the (possible) TLB refills
+ * to work correctly.
+ */
+ page = (KSEG0 + (page & (dcache_size - 1)));
+ if (cpu_has_dc_aliases || exec)
+ tx39_blast_dcache_page_indexed(page);
+ if (exec)
+ tx39_blast_icache_page_indexed(page);
}
-static void tx39_flush_page_to_ram(struct page * page)
+static void tx39_flush_data_cache_page(unsigned long addr)
{
- blast_dcache16_page((unsigned long)page_address(page));
+ tx39_blast_dcache_page(addr);
}
static void tx39_flush_icache_range(unsigned long start, unsigned long end)
{
- flush_cache_all();
+ unsigned long dc_lsize = current_cpu_data.dcache.linesz;
+ unsigned long addr, aend;
+
+ if (end - start > dcache_size)
+ tx39_blast_dcache();
+ else {
+ addr = start & ~(dc_lsize - 1);
+ aend = (end - 1) & ~(dc_lsize - 1);
+
+ while (1) {
+ /* Hit_Writeback_Inv_D */
+ protected_writeback_dcache_line(addr);
+ if (addr == aend)
+ break;
+ addr += dc_lsize;
+ }
+ }
+
+ if (end - start > icache_size)
+ tx39_blast_icache();
+ else {
+ unsigned long flags, config;
+ addr = start & ~(dc_lsize - 1);
+ aend = (end - 1) & ~(dc_lsize - 1);
+ /* disable icache (set ICE#) */
+ local_irq_save(flags);
+ config = read_c0_conf();
+ write_c0_conf(config & ~TX39_CONF_ICE);
+ TX39_STOP_STREAMING();
+ while (1) {
+ /* Hit_Invalidate_I */
+ protected_flush_icache_line(addr);
+ if (addr == aend)
+ break;
+ addr += dc_lsize;
+ }
+ write_c0_conf(config);
+ local_irq_restore(flags);
+ }
}
+/*
+ * Ok, this seriously sucks. We use them to flush a user page but don't
+ * know the virtual address, so we have to blast away the whole icache
+ * which is significantly more expensive than the real thing. Otoh we at
+ * least know the kernel address of the page so we can flush it
+ * selectivly.
+ */
static void tx39_flush_icache_page(struct vm_area_struct *vma, struct page *page)
{
+ unsigned long addr;
+ /*
+ * If there's no context yet, or the page isn't executable, no icache
+ * flush is needed.
+ */
if (!(vma->vm_flags & VM_EXEC))
return;
- flush_cache_all();
+ addr = (unsigned long) page_address(page);
+ tx39_blast_dcache_page(addr);
+
+ /*
+ * We're not sure of the virtual address(es) involved here, so
+ * we have to flush the entire I-cache.
+ */
+ tx39_blast_icache();
}
static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
unsigned long end, a;
- if (size >= dcache_size) {
- flush_cache_all();
+ if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
+ end = addr + size;
+ do {
+ tx39_blast_dcache_page(addr);
+ addr += PAGE_SIZE;
+ } while(addr != end);
+ } else if (size > dcache_size) {
+ tx39_blast_dcache();
} else {
- a = addr & ~(dcache_lsize - 1);
- end = (addr + size) & ~(dcache_lsize - 1);
+ unsigned long dc_lsize = current_cpu_data.dcache.linesz;
+ a = addr & ~(dc_lsize - 1);
+ end = (addr + size - 1) & ~(dc_lsize - 1);
while (1) {
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
if (a == end) break;
- a += dcache_lsize;
+ a += dc_lsize;
}
}
}
@@ -211,59 +334,75 @@
{
unsigned long end, a;
- if (size >= dcache_size) {
- flush_cache_all();
+ if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
+ end = addr + size;
+ do {
+ tx39_blast_dcache_page(addr);
+ addr += PAGE_SIZE;
+ } while(addr != end);
+ } else if (size > dcache_size) {
+ tx39_blast_dcache();
} else {
- a = addr & ~(dcache_lsize - 1);
- end = (addr + size) & ~(dcache_lsize - 1);
+ unsigned long dc_lsize = current_cpu_data.dcache.linesz;
+ a = addr & ~(dc_lsize - 1);
+ end = (addr + size - 1) & ~(dc_lsize - 1);
while (1) {
invalidate_dcache_line(a); /* Hit_Invalidate_D */
if (a == end) break;
- a += dcache_lsize;
+ a += dc_lsize;
}
}
}
-static void tx39_dma_cache_wback(unsigned long addr, unsigned long size)
-{
- panic("tx39_dma_cache called - should not happen.");
-}
-
static void tx39_flush_cache_sigtramp(unsigned long addr)
{
+ unsigned long ic_lsize = current_cpu_data.icache.linesz;
+ unsigned long dc_lsize = current_cpu_data.dcache.linesz;
unsigned long config;
- unsigned int flags;
+ unsigned long flags;
- __save_and_cli(flags);
- protected_writeback_dcache_line(addr & ~(dcache_lsize - 1));
+ protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
/* disable icache (set ICE#) */
- config = read_32bit_cp0_register(CP0_CONF);
- write_32bit_cp0_register(CP0_CONF, config&~TX39_CONF_ICE);
- protected_flush_icache_line(addr & ~(icache_lsize - 1));
- write_32bit_cp0_register(CP0_CONF, config);
- __restore_flags(flags);
+ local_irq_save(flags);
+ config = read_c0_conf();
+ write_c0_conf(config & ~TX39_CONF_ICE);
+ TX39_STOP_STREAMING();
+ protected_flush_icache_line(addr & ~(ic_lsize - 1));
+ write_c0_conf(config);
+ local_irq_restore(flags);
}
static __init void tx39_probe_cache(void)
{
unsigned long config;
- config = read_32bit_cp0_register(CP0_CONF);
+ config = read_c0_conf();
- icache_size = 1 << (10 + ((config >> 19) & 3));
- dcache_size = 1 << (10 + ((config >> 16) & 3));
+ icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
+ TX39_CONF_ICS_SHIFT));
+ dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
+ TX39_CONF_DCS_SHIFT));
- icache_lsize = 16;
- switch (mips_cpu.cputype) {
+ current_cpu_data.icache.linesz = 16;
+ switch (current_cpu_data.cputype) {
case CPU_TX3912:
- dcache_lsize = 4;
+ current_cpu_data.icache.ways = 1;
+ current_cpu_data.dcache.ways = 1;
+ current_cpu_data.dcache.linesz = 4;
break;
- case CPU_TX3922:
+
case CPU_TX3927:
- case CPU_TX39XX:
+ current_cpu_data.icache.ways = 2;
+ current_cpu_data.dcache.ways = 2;
+ current_cpu_data.dcache.linesz = 16;
+ break;
+
+ case CPU_TX3922:
default:
- dcache_lsize = 16;
+ current_cpu_data.icache.ways = 1;
+ current_cpu_data.dcache.ways = 1;
+ current_cpu_data.dcache.linesz = 16;
break;
}
}
@@ -275,13 +414,13 @@
_clear_page = r3k_clear_page;
_copy_page = r3k_copy_page;
- config = read_32bit_cp0_register(CP0_CONF);
+ config = read_c0_conf();
config &= ~TX39_CONF_WBON;
- write_32bit_cp0_register(CP0_CONF, config);
+ write_c0_conf(config);
tx39_probe_cache();
- switch (mips_cpu.cputype) {
+ switch (current_cpu_data.cputype) {
case CPU_TX3912:
/* TX39/H core (writethru direct-map cache) */
_flush_cache_all = tx39h_flush_icache_all;
@@ -289,12 +428,16 @@
_flush_cache_mm = (void *) tx39h_flush_icache_all;
_flush_cache_range = (void *) tx39h_flush_icache_all;
_flush_cache_page = (void *) tx39h_flush_icache_all;
- _flush_cache_sigtramp = (void *) tx39h_flush_icache_all;
- _flush_page_to_ram = tx39h_flush_page_to_ram;
_flush_icache_page = (void *) tx39h_flush_icache_all;
_flush_icache_range = (void *) tx39h_flush_icache_all;
- _dma_cache_wback_inv = tx39h_dma_cache_wback_inv;
+ _flush_cache_sigtramp = (void *) tx39h_flush_icache_all;
+ _flush_data_cache_page = (void *) tx39h_flush_icache_all;
+
+ _dma_cache_wback_inv = tx39h_dma_cache_wback_inv;
+
+ shm_align_mask = PAGE_SIZE - 1;
+
break;
case CPU_TX3922:
@@ -302,37 +445,47 @@
default:
/* TX39/H2,H3 core (writeback 2way-set-associative cache) */
r3k_have_wired_reg = 1;
- set_wired (0); /* set 8 on reset... */
+ write_c0_wired(0); /* set 8 on reset... */
/* board-dependent init code may set WBON */
_flush_cache_all = tx39_flush_cache_all;
- ___flush_cache_all = tx39_flush_cache_all;
+ ___flush_cache_all = tx39___flush_cache_all;
_flush_cache_mm = tx39_flush_cache_mm;
_flush_cache_range = tx39_flush_cache_range;
_flush_cache_page = tx39_flush_cache_page;
- _flush_cache_sigtramp = tx39_flush_cache_sigtramp;
- _flush_page_to_ram = tx39_flush_page_to_ram;
_flush_icache_page = tx39_flush_icache_page;
_flush_icache_range = tx39_flush_icache_range;
+ _flush_cache_sigtramp = tx39_flush_cache_sigtramp;
+ _flush_data_cache_page = tx39_flush_data_cache_page;
+
_dma_cache_wback_inv = tx39_dma_cache_wback_inv;
- _dma_cache_wback = tx39_dma_cache_wback;
+ _dma_cache_wback = tx39_dma_cache_wback_inv;
_dma_cache_inv = tx39_dma_cache_inv;
+ shm_align_mask = max_t(unsigned long,
+ (dcache_size / current_cpu_data.dcache.ways) - 1,
+ PAGE_SIZE - 1);
+
break;
}
- if (mips_cpu.icache.ways == 0)
- mips_cpu.icache.ways = 1;
- if (mips_cpu.dcache.ways == 0)
- mips_cpu.dcache.ways = 1;
- mips_cpu.icache.sets =
- icache_size / mips_cpu.icache.ways / mips_cpu.icache.linesz;
- mips_cpu.dcache.sets =
- dcache_size / mips_cpu.dcache.ways / mips_cpu.dcache.linesz;
-
- printk("Primary instruction cache %dkb, linesize %d bytes\n",
- (int) (icache_size >> 10), (int) icache_lsize);
- printk("Primary data cache %dkb, linesize %d bytes\n",
- (int) (dcache_size >> 10), (int) dcache_lsize);
+ current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
+ current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;
+
+ current_cpu_data.icache.sets =
+ current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
+ current_cpu_data.dcache.sets =
+ current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;
+
+ if (current_cpu_data.dcache.waysize > PAGE_SIZE)
+ current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;
+
+ current_cpu_data.icache.waybit = 0;
+ current_cpu_data.dcache.waybit = 0;
+
+ printk("Primary instruction cache %ldkb, linesize %d bytes\n",
+ icache_size >> 10, current_cpu_data.icache.linesz);
+ printk("Primary data cache %ldkb, linesize %d bytes\n",
+ dcache_size >> 10, current_cpu_data.dcache.linesz);
}
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