patch-2.4.22 linux-2.4.22/arch/mips/vr4181/common/irq.c
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- Lines: 48
- Date:
2003-08-25 04:44:40.000000000 -0700
- Orig file:
linux-2.4.21/arch/mips/vr4181/common/irq.c
- Orig date:
2002-08-02 17:39:43.000000000 -0700
diff -urN linux-2.4.21/arch/mips/vr4181/common/irq.c linux-2.4.22/arch/mips/vr4181/common/irq.c
@@ -7,7 +7,7 @@
*
* Credits to Bradley D. LaRonde and Michael Klar for writing the original
* irq.c file which was derived from the common irq.c file.
- *
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
@@ -180,9 +180,9 @@
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
extern void mips_cpu_irq_init(u32 irq_base);
-static struct irqaction cascade =
+static struct irqaction cascade =
{ no_action, SA_INTERRUPT, 0, "cascade", NULL, NULL };
-static struct irqaction reserved =
+static struct irqaction reserved =
{ no_action, SA_INTERRUPT, 0, "cascade", NULL, NULL };
void __init init_IRQ(void)
@@ -216,7 +216,7 @@
/* Default all ICU IRQs to off ... */
*VR4181_MSYSINT1REG = 0;
*VR4181_MSYSINT2REG = 0;
-
+
/* We initialize the level 2 ICU registers to all bits disabled. */
*VR4181_MPIUINTREG = 0;
*VR4181_MAIUINTREG = 0;
@@ -229,7 +229,7 @@
setup_irq(VR4181_IRQ_INT0, &cascade);
setup_irq(VR4181_IRQ_GIU, &cascade);
- /*
+ /*
* RTC interrupts are interesting. They have two destinations.
* One is at sys irq controller, and the other is at CPU IP3 and IP4.
* RTC timer is used as system timer.
@@ -239,7 +239,7 @@
setup_irq(VR4181_IRQ_RTCL1, &reserved);
setup_irq(VR4181_IRQ_RTCL2, &reserved);
-#ifdef CONFIG_REMOTE_DEBUG
+#ifdef CONFIG_KGDB
printk("Setting debug traps - please connect the remote debugger.\n");
set_debug_traps();
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