patch-2.4.22 linux-2.4.22/arch/ppc/platforms/pmac_sleep.S
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- Lines: 68
- Date:
2003-08-25 04:44:40.000000000 -0700
- Orig file:
linux-2.4.21/arch/ppc/platforms/pmac_sleep.S
- Orig date:
2003-06-13 07:51:31.000000000 -0700
diff -urN linux-2.4.21/arch/ppc/platforms/pmac_sleep.S linux-2.4.22/arch/ppc/platforms/pmac_sleep.S
@@ -74,7 +74,7 @@
mftbu r3
cmpw r3,r4
bne 1b
-
+
/* Save SPRGs */
mfsprg r4,0
stw r4,SL_SPRG0(r1)
@@ -162,7 +162,7 @@
sync
mtspr SPRN_HID0,r3
sync
-
+
/* Turn off data relocation. */
mfmsr r3 /* Save MSR in r7 */
rlwinm r3,r3,0,28,26 /* Turn off DR bit */
@@ -197,7 +197,7 @@
isync
b 1b
-/*
+/*
* Here is the resume code.
*/
@@ -217,7 +217,7 @@
/* Won't that cause problems on CPU that doesn't support it ? */
lis r3, 0
mtspr SPRN_MMCR0, r3
-
+
/* sanitize MSR */
mfmsr r3
ori r3,r3,MSR_EE|MSR_IP
@@ -235,11 +235,11 @@
lwz r1,0(r3)
/* Pass thru to older resume code ... */
-/*
+/*
* Here is the resume code for older machines.
* r1 has the physical address of SL_PC(sp).
*/
-
+
grackle_wake_up:
/* Invalidate & enable L1 cache, we don't care about
* whatever the ROM may have tried to write to memory
@@ -260,7 +260,7 @@
bdnz 3b
sync
isync
-
+
subi r1,r1,SL_PC
/* Restore various CPU config stuffs */
@@ -340,7 +340,7 @@
/* restore the MSR and turn on the MMU */
lwz r3,SL_MSR(r1)
- bl turn_on_mmu
+ bl turn_on_mmu
/* get back the stack pointer */
tovirt(r1,r1)
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