patch-2.4.22 linux-2.4.22/include/asm-alpha/core_t2.h

• Lines: 189
• Date: 2003-08-25 04:44:43.000000000 -0700
• Orig file: linux-2.4.21/include/asm-alpha/core_t2.h
• Orig date: 2003-06-13 07:51:38.000000000 -0700

diff -urN linux-2.4.21/include/asm-alpha/core_t2.h linux-2.4.22/include/asm-alpha/core_t2.h
@@ -3,8 +3,9 @@
 
 #include <linux/config.h>
 #include <linux/types.h>
+#include <linux/spinlock.h>
 #include <asm/compiler.h>
-
+#include <asm/system.h>
 
 /*
  * T2 is the internal name for the core logic chipset which provides
@@ -22,6 +23,7 @@
 #define T2_MEM_R1_MASK 0x07ffffff  /* Mem sparse region 1 mask is 26 bits */
 
 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */
+/* All LYNX machines, EV4 or EV5, use the GAMMA bias also */
 #define _GAMMA_BIAS		0x8000000000UL
 
 #if defined(CONFIG_ALPHA_GENERIC)
@@ -57,10 +59,33 @@
 #define T2_WMASK2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
 #define T2_TBASE2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
 #define T2_TLBBR		(IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
-
+#define T2_IVR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL)
 #define T2_HAE_3		(IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
 #define T2_HAE_4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
 
+/* The CSRs below are T3/T4 only */
+#define T2_WBASE3		(IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL)
+#define T2_WMASK3		(IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL)
+#define T2_TBASE3		(IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL)
+
+#define T2_TDR0			(IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL)
+#define T2_TDR1			(IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL)
+#define T2_TDR2			(IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL)
+#define T2_TDR3			(IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL)
+#define T2_TDR4			(IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL)
+#define T2_TDR5			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL)
+#define T2_TDR6			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL)
+#define T2_TDR7			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL)
+
+#define T2_WBASE4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL)
+#define T2_WMASK4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL)
+#define T2_TBASE4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL)
+
+#define T2_AIR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL)
+#define T2_VAR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL)
+#define T2_DIR			(IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL)
+#define T2_ICE			(IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL)
+
 #define T2_HAE_ADDRESS		T2_HAE_1
 
 /*  T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
@@ -100,6 +125,9 @@
 #define T2_CPU1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x381000000L)
 #define T2_CPU2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x382000000L)
 #define T2_CPU3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x383000000L)
+
+#define T2_CPUn_BASE(n)		(T2_CPU0_BASE + (((n)&3) * 0x001000000L))
+
 #define T2_MEM0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x388000000L)
 #define T2_MEM1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x389000000L)
 #define T2_MEM2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L)
@@ -408,87 +436,120 @@
 	set_hae(msb); \
 }
 
+static spinlock_t t2_hae_lock = SPIN_LOCK_UNLOCKED;
+
 __EXTERN_INLINE u8 t2_readb(unsigned long addr)
 {
 	unsigned long result, msb;
+	unsigned long flags;
+	spin_lock_irqsave(&t2_hae_lock, flags);
 
 	t2_set_hae;
 
 	result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00);
+	spin_unlock_irqrestore(&t2_hae_lock, flags);
 	return __kernel_extbl(result, addr & 3);
 }
 
 __EXTERN_INLINE u16 t2_readw(unsigned long addr)
 {
 	unsigned long result, msb;
+	unsigned long flags;
+	spin_lock_irqsave(&t2_hae_lock, flags);
 
 	t2_set_hae;
 
 	result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);
+	spin_unlock_irqrestore(&t2_hae_lock, flags);
 	return __kernel_extwl(result, addr & 3);
 }
 
-/* On SABLE with T2, we must use SPARSE memory even for 32-bit access. */
+/*
+ * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
+ * because we cannot access all of DENSE without changing its HAE.
+ */
 __EXTERN_INLINE u32 t2_readl(unsigned long addr)
 {
-	unsigned long msb;
+	unsigned long result, msb;
+	unsigned long flags;
+	spin_lock_irqsave(&t2_hae_lock, flags);
 
 	t2_set_hae;
 
-	return *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
+	result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
+	spin_unlock_irqrestore(&t2_hae_lock, flags);
+	return result & 0xffffffffUL;
 }
 
 __EXTERN_INLINE u64 t2_readq(unsigned long addr)
 {
 	unsigned long r0, r1, work, msb;
+	unsigned long flags;
+	spin_lock_irqsave(&t2_hae_lock, flags);
 
 	t2_set_hae;
 
 	work = (addr << 5) + T2_SPARSE_MEM + 0x18;
 	r0 = *(vuip)(work);
 	r1 = *(vuip)(work + (4 << 5));
+	spin_unlock_irqrestore(&t2_hae_lock, flags);
 	return r1 << 32 | r0;
 }
 
 __EXTERN_INLINE void t2_writeb(u8 b, unsigned long addr)
 {
 	unsigned long msb, w;
+	unsigned long flags;
+	spin_lock_irqsave(&t2_hae_lock, flags);
 
 	t2_set_hae;
 
 	w = __kernel_insbl(b, addr & 3);
 	*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;
+	spin_unlock_irqrestore(&t2_hae_lock, flags);
 }
 
 __EXTERN_INLINE void t2_writew(u16 b, unsigned long addr)
 {
 	unsigned long msb, w;
+	unsigned long flags;
+	spin_lock_irqsave(&t2_hae_lock, flags);
 
 	t2_set_hae;
 
 	w = __kernel_inswl(b, addr & 3);
 	*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;
+	spin_unlock_irqrestore(&t2_hae_lock, flags);
 }
 
-/* On SABLE with T2, we must use SPARSE memory even for 32-bit access. */
+/*
+ * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
+ * because we cannot access all of DENSE without changing its HAE.
+ */
 __EXTERN_INLINE void t2_writel(u32 b, unsigned long addr)
 {
 	unsigned long msb;
+	unsigned long flags;
+	spin_lock_irqsave(&t2_hae_lock, flags);
 
 	t2_set_hae;
 
 	*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;
+	spin_unlock_irqrestore(&t2_hae_lock, flags);
 }
 
 __EXTERN_INLINE void t2_writeq(u64 b, unsigned long addr)
 {
 	unsigned long msb, work;
+	unsigned long flags;
+	spin_lock_irqsave(&t2_hae_lock, flags);
 
 	t2_set_hae;
 
 	work = (addr << 5) + T2_SPARSE_MEM + 0x18;
 	*(vuip)work = b;
 	*(vuip)(work + (4 << 5)) = b >> 32;
+	spin_unlock_irqrestore(&t2_hae_lock, flags);
 }
 
 __EXTERN_INLINE unsigned long t2_ioremap(unsigned long addr,