patch-2.4.22 linux-2.4.22/include/asm-mips64/io.h
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- Lines: 459
- Date:
2003-08-25 04:44:44.000000000 -0700
- Orig file:
linux-2.4.21/include/asm-mips64/io.h
- Orig date:
2002-11-28 15:53:15.000000000 -0800
diff -urN linux-2.4.21/include/asm-mips64/io.h linux-2.4.22/include/asm-mips64/io.h
@@ -15,6 +15,10 @@
#include <asm/page.h>
#include <asm/byteorder.h>
+#ifdef CONFIG_DECSTATION
+#include <asm/dec/io.h>
+#endif
+
#ifdef CONFIG_MIPS_ATLAS
#include <asm/mips-boards/io.h>
#endif
@@ -23,6 +27,10 @@
#include <asm/mips-boards/io.h>
#endif
+#ifdef CONFIG_MIPS_SEAD
+#include <asm/mips-boards/io.h>
+#endif
+
#ifdef CONFIG_SGI_IP22
#include <asm/sgi/io.h>
#endif
@@ -31,22 +39,20 @@
#include <asm/sn/io.h>
#endif
-#ifdef CONFIG_SGI_IP32
-#include <asm/ip32/io.h>
-#endif
-
-#ifdef CONFIG_SIBYTE_SB1250
+#ifdef CONFIG_SIBYTE_SB1xxx_SOC
#include <asm/sibyte/io.h>
#endif
#ifdef CONFIG_SGI_IP27
extern unsigned long bus_to_baddr[256];
-#define bus_to_baddr(hwdev, addr) (bus_to_baddr[(hwdev)->bus->number] + (addr))
-#define baddr_to_bus(hwdev, addr) ((addr) - bus_to_baddr[(hwdev)->bus->number])
+#define bus_to_baddr(bus, addr) (bus_to_baddr[(bus)->number] + (addr))
+#define baddr_to_bus(bus, addr) ((addr) - bus_to_baddr[(bus)->number])
+#define __swizzle_addr_w(port) ((port) ^ 2)
#else
-#define bus_to_baddr(hwdev, addr) (addr)
-#define baddr_to_bus(hwdev, addr) (addr)
+#define bus_to_baddr(bus, addr) (addr)
+#define baddr_to_bus(bus, addr) (addr)
+#define __swizzle_addr_w(port) (port)
#endif
/*
@@ -56,26 +62,24 @@
/*
* Sane hardware offers swapping of I/O space accesses in hardware; less
- * sane hardware forces software to fiddle with this ...
+ * sane hardware forces software to fiddle with this. Totally insane hardware
+ * introduces special cases like:
+ *
+ * IP22 seems braindead enough to swap 16-bits values in hardware, but not
+ * 32-bits. Go figure... Can't tell without documentation.
+ *
+ * We only do the swapping to keep the kernel config bits of bi-endian
+ * machines a bit saner.
*/
-#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
-
-#define __ioswab8(x) (x)
-#ifdef CONFIG_SGI_IP22
-/* IP22 seems braindead enough to swap 16bits values in hardware, but
- not 32bits. Go figure... Can't tell without documentation. */
-#define __ioswab16(x) (x)
-#else
+#if defined(CONFIG_SWAP_IO_SPACE_W) && defined(__MIPSEB__)
#define __ioswab16(x) swab16(x)
+#else
+#define __ioswab16(x) (x)
#endif
+#if defined(CONFIG_SWAP_IO_SPACE_L) && defined(__MIPSEB__)
#define __ioswab32(x) swab32(x)
-
#else
-
-#define __ioswab8(x) (x)
-#define __ioswab16(x) (x)
#define __ioswab32(x) (x)
-
#endif
/*
@@ -127,6 +131,11 @@
{
}
+/*
+ * XXX We need system specific versions of these to handle EISA address bits
+ * 24-31 on SNI.
+ * XXX more SNI hacks.
+ */
#define readb(addr) (*(volatile unsigned char *)(addr))
#define readw(addr) __ioswab16((*(volatile unsigned short *)(addr)))
#define readl(addr) __ioswab32((*(volatile unsigned int *)(addr)))
@@ -135,7 +144,7 @@
#define __raw_readw(addr) (*(volatile unsigned short *)(addr))
#define __raw_readl(addr) (*(volatile unsigned int *)(addr))
-#define writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (__ioswab8(b)))
+#define writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (b))
#define writew(b,addr) ((*(volatile unsigned short *)(addr)) = (__ioswab16(b)))
#define writel(b,addr) ((*(volatile unsigned int *)(addr)) = (__ioswab32(b)))
@@ -143,93 +152,13 @@
#define __raw_writew(w,addr) ((*(volatile unsigned short *)(addr)) = (w))
#define __raw_writel(l,addr) ((*(volatile unsigned int *)(addr)) = (l))
+/*
+ * TODO: Should use variants that don't do prefetching.
+ */
#define memset_io(a,b,c) memset((void *)(a),(b),(c))
#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
-/* The ISA versions are supplied by system specific code */
-
-/*
- * On MIPS I/O ports are memory mapped, so we access them using normal
- * load/store instructions. mips_io_port_base is the virtual address to
- * which all ports are being mapped. For sake of efficiency some code
- * assumes that this is an address that can be loaded with a single lui
- * instruction, so the lower 16 bits must be zero. Should be true on
- * on any sane architecture; generic code does not use this assumption.
- */
-extern const unsigned long mips_io_port_base;
-
-#define set_io_port_base(base) \
- do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
-
-#define __SLOW_DOWN_IO \
- __asm__ __volatile__( \
- "sb\t$0,0x80(%0)" \
- : : "r" (mips_io_port_base));
-
-#ifdef CONF_SLOWDOWN_IO
-#ifdef REALLY_SLOW_IO
-#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
-#else
-#define SLOW_DOWN_IO __SLOW_DOWN_IO
-#endif
-#else
-#define SLOW_DOWN_IO
-#endif
-
-/*
- * virt_to_phys - map virtual addresses to physical
- * @address: address to remap
- *
- * The returned physical address is the physical (CPU) mapping for
- * the memory address given. It is only valid to use this function on
- * addresses directly mapped or allocated via kmalloc.
- *
- * This function does not give bus mappings for DMA transfers. In
- * almost all conceivable cases a device driver should not be using
- * this function
- */
-
-static inline unsigned long virt_to_phys(volatile void * address)
-{
- return (unsigned long)address - PAGE_OFFSET;
-}
-
-/*
- * phys_to_virt - map physical address to virtual
- * @address: address to remap
- *
- * The returned virtual address is a current CPU mapping for
- * the memory address given. It is only valid to use this function on
- * addresses that have a kernel mapping
- *
- * This function does not handle bus mappings for DMA transfers. In
- * almost all conceivable cases a device driver should not be using
- * this function
- */
-
-static inline void * phys_to_virt(unsigned long address)
-{
- return (void *)(address + PAGE_OFFSET);
-}
-
-/*
- * IO bus memory addresses are also 1:1 with the physical address
- */
-static inline unsigned long virt_to_bus(volatile void * address)
-{
- return (unsigned long)address - PAGE_OFFSET;
-}
-
-static inline void * bus_to_virt(unsigned long address)
-{
- return (void *)(address + PAGE_OFFSET);
-}
-
-
-/* This is too simpleminded for more sophisticated than dumb hardware ... */
-#define page_to_bus page_to_phys
-
/*
* isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
* for the processor. This implies the assumption that there is only
@@ -262,6 +191,7 @@
* just copy it. The net code will then do the checksum later.
*/
#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
+#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
/*
* check_signature - find BIOS signatures
@@ -273,9 +203,8 @@
* address should have been obtained by ioremap.
* Returns 1 on a match.
*/
-static inline int
-check_signature(unsigned long io_addr, const unsigned char *signature,
- int length)
+static inline int check_signature(unsigned long io_addr,
+ const unsigned char *signature, int length)
{
int retval = 0;
do {
@@ -319,14 +248,95 @@
return retval;
}
+/*
+ * virt_to_phys - map virtual addresses to physical
+ * @address: address to remap
+ *
+ * The returned physical address is the physical (CPU) mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses directly mapped or allocated via kmalloc.
+ *
+ * This function does not give bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
+ */
+
+static inline unsigned long virt_to_phys(volatile void * address)
+{
+ return (unsigned long)address - PAGE_OFFSET;
+}
+
+/*
+ * phys_to_virt - map physical address to virtual
+ * @address: address to remap
+ *
+ * The returned virtual address is a current CPU mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses that have a kernel mapping
+ *
+ * This function does not handle bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
+ */
+
+static inline void * phys_to_virt(unsigned long address)
+{
+ return (void *)(address + PAGE_OFFSET);
+}
+
+/*
+ * IO bus memory addresses are also 1:1 with the physical address
+ */
+static inline unsigned long virt_to_bus(volatile void * address)
+{
+ return (unsigned long)address - PAGE_OFFSET;
+}
+
+static inline void * bus_to_virt(unsigned long address)
+{
+ return (void *)(address + PAGE_OFFSET);
+}
+
+/* This is too simpleminded for more sophisticated than dumb hardware ... */
+#define page_to_bus page_to_phys
+
+/*
+ * On MIPS I/O ports are memory mapped, so we access them using normal
+ * load/store instructions. mips_io_port_base is the virtual address to
+ * which all ports are being mapped. For sake of efficiency some code
+ * assumes that this is an address that can be loaded with a single lui
+ * instruction, so the lower 16 bits must be zero. Should be true on
+ * on any sane architecture; generic code does not use this assumption.
+ */
+extern const unsigned long mips_io_port_base;
+
+#define set_io_port_base(base) \
+ do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
+
+#define __SLOW_DOWN_IO \
+ __asm__ __volatile__( \
+ "sb\t$0,0x80(%0)" \
+ : : "r" (mips_io_port_base));
+
+#ifdef CONF_SLOWDOWN_IO
+#ifdef REALLY_SLOW_IO
+#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
+#else
+#define SLOW_DOWN_IO __SLOW_DOWN_IO
+#endif
+#else
+#define SLOW_DOWN_IO
+#endif
+
#define outb(val,port) \
do { \
- *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \
+ *(volatile u8 *)(mips_io_port_base + (port)) = (val); \
} while(0)
#define outw(val,port) \
do { \
- *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\
+ *(volatile u16 *)(mips_io_port_base + __swizzle_addr_w(port)) = \
+ __ioswab16(val); \
} while(0)
#define outl(val,port) \
@@ -336,13 +346,14 @@
#define outb_p(val,port) \
do { \
- *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \
+ *(volatile u8 *)(mips_io_port_base + (port)) = (val); \
SLOW_DOWN_IO; \
} while(0)
#define outw_p(val,port) \
do { \
- *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\
+ *(volatile u16 *)(mips_io_port_base + __swizzle_addr_w(port)) = \
+ __ioswab16(val); \
SLOW_DOWN_IO; \
} while(0)
@@ -354,11 +365,13 @@
static inline unsigned char inb(unsigned long port)
{
- return __ioswab8(*(volatile u8 *)(mips_io_port_base + port));
+ return *(volatile u8 *)(mips_io_port_base + port);
}
static inline unsigned short inw(unsigned long port)
{
+ port = __swizzle_addr_w(port);
+
return __ioswab16(*(volatile u16 *)(mips_io_port_base + port));
}
@@ -374,13 +387,14 @@
__val = *(volatile u8 *)(mips_io_port_base + port);
SLOW_DOWN_IO;
- return __ioswab8(__val);
+ return __val;
}
static inline unsigned short inw_p(unsigned long port)
{
u16 __val;
+ port = __swizzle_addr_w(port);
__val = *(volatile u16 *)(mips_io_port_base + port);
SLOW_DOWN_IO;
@@ -396,7 +410,7 @@
return __ioswab32(__val);
}
-static inline void outsb(unsigned long port, void *addr, unsigned int count)
+static inline void __outsb(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
outb(*(u8 *)addr, port);
@@ -404,7 +418,7 @@
}
}
-static inline void insb(unsigned long port, void *addr, unsigned int count)
+static inline void __insb(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
*(u8 *)addr = inb(port);
@@ -412,7 +426,7 @@
}
}
-static inline void outsw(unsigned long port, void *addr, unsigned int count)
+static inline void __outsw(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
outw(*(u16 *)addr, port);
@@ -420,7 +434,7 @@
}
}
-static inline void insw(unsigned long port, void *addr, unsigned int count)
+static inline void __insw(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
*(u16 *)addr = inw(port);
@@ -428,7 +442,7 @@
}
}
-static inline void outsl(unsigned long port, void *addr, unsigned int count)
+static inline void __outsl(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
outl(*(u32 *)addr, port);
@@ -436,7 +450,7 @@
}
}
-static inline void insl(unsigned long port, void *addr, unsigned int count)
+static inline void __insl(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
*(u32 *)addr = inl(port);
@@ -444,6 +458,13 @@
}
}
+#define outsb(port, addr, count) __outsb(port, addr, count)
+#define insb(port, addr, count) __insb(port, addr, count)
+#define outsw(port, addr, count) __outsw(port, addr, count)
+#define insw(port, addr, count) __insw(port, addr, count)
+#define outsl(port, addr, count) __outsl(port, addr, count)
+#define insl(port, addr, count) __insl(port, addr, count)
+
/*
* The caches on some architectures aren't dma-coherent and have need to
* handle this in software. There are three types of operations that
@@ -474,9 +495,12 @@
#else /* Sane hardware */
-#define dma_cache_wback_inv(start,size) do { (start); (size); } while (0)
-#define dma_cache_wback(start,size) do { (start); (size); } while (0)
-#define dma_cache_inv(start,size) do { (start); (size); } while (0)
+#define dma_cache_wback_inv(start,size) \
+ do { (void) (start); (void) (size); } while (0)
+#define dma_cache_wback(start,size) \
+ do { (void) (start); (void) (size); } while (0)
+#define dma_cache_inv(start,size) \
+ do { (void) (start); (void) (size); } while (0)
#endif /* CONFIG_NONCOHERENT_IO */
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