patch-2.4.25 linux-2.4.25/arch/mips/vr41xx/common/cmu.c
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- Lines: 209
- Date:
2004-02-18 05:36:30.000000000 -0800
- Orig file:
linux-2.4.24/arch/mips/vr41xx/common/cmu.c
- Orig date:
2003-08-25 04:44:40.000000000 -0700
diff -urN linux-2.4.24/arch/mips/vr41xx/common/cmu.c linux-2.4.25/arch/mips/vr41xx/common/cmu.c
@@ -33,52 +33,192 @@
/*
* Changes:
* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
+ * - New creation, NEC VR4122 and VR4131 are supported.
* - Added support for NEC VR4111 and VR4121.
*
- * MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
- * - New creation, NEC VR4122 and VR4131 are supported.
+ * Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ * - Added support for NEC VR4133.
*/
#include <linux/init.h>
#include <linux/types.h>
#include <asm/cpu.h>
#include <asm/io.h>
+#include <asm/vr41xx/vr41xx.h>
-#define VR4111_CMUCLKMSK KSEG1ADDR(0x0b000060)
-#define VR4122_CMUCLKMSK KSEG1ADDR(0x0f000060)
+#define CMUCLKMSK_TYPE1 KSEG1ADDR(0x0b000060)
+#define CMUCLKMSK_TYPE2 KSEG1ADDR(0x0f000060)
+ #define MSKPIU 0x0001
+ #define MSKSIU 0x0002
+ #define MSKAIU 0x0004
+ #define MSKKIU 0x0008
+ #define MSKFIR 0x0010
+ #define MSKDSIU 0x0820
+ #define MSKCSI 0x0040
+ #define MSKPCIU 0x0080
+ #define MSKSSIU 0x0100
+ #define MSKSHSP 0x0200
+ #define MSKFFIR 0x0400
+ #define MSKSCSI 0x1000
+ #define MSKPPCIU 0x2000
+#define CMUCLKMSK2 KSEG1ADDR(0x0f000064)
+ #define MSKCEU 0x0001
+ #define MSKMAC0 0x0002
+ #define MSKMAC1 0x0004
static u32 vr41xx_cmu_base;
-static u16 cmuclkmsk;
+static u16 cmuclkmsk, cmuclkmsk2;
-#define write_cmu(mask) writew((mask), vr41xx_cmu_base)
+#define read_cmuclkmsk() readw(vr41xx_cmu_base)
+#define read_cmuclkmsk2() readw(CMUCLKMSK2)
+#define write_cmuclkmsk() writew(cmuclkmsk, vr41xx_cmu_base)
+#define write_cmuclkmsk2() writew(cmuclkmsk2, CMUCLKMSK2)
-void vr41xx_clock_supply(u16 mask)
+void vr41xx_clock_supply(unsigned int clock)
{
- cmuclkmsk |= mask;
- write_cmu(cmuclkmsk);
+ switch (clock) {
+ case PIU_CLOCK:
+ cmuclkmsk |= MSKPIU;
+ break;
+ case SIU_CLOCK:
+ cmuclkmsk |= MSKSIU | MSKSSIU;
+ break;
+ case AIU_CLOCK:
+ cmuclkmsk |= MSKAIU;
+ break;
+ case KIU_CLOCK:
+ cmuclkmsk |= MSKKIU;
+ break;
+ case FIR_CLOCK:
+ cmuclkmsk |= MSKFIR | MSKFFIR;
+ break;
+ case DSIU_CLOCK:
+ if (current_cpu_data.cputype == CPU_VR4111 ||
+ current_cpu_data.cputype == CPU_VR4121)
+ cmuclkmsk |= MSKDSIU;
+ else
+ cmuclkmsk |= MSKSIU | MSKDSIU;
+ break;
+ case CSI_CLOCK:
+ cmuclkmsk |= MSKCSI | MSKSCSI;
+ break;
+ case PCIU_CLOCK:
+ cmuclkmsk |= MSKPCIU;
+ break;
+ case HSP_CLOCK:
+ cmuclkmsk |= MSKSHSP;
+ break;
+ case PCI_CLOCK:
+ cmuclkmsk |= MSKPPCIU;
+ break;
+ case CEU_CLOCK:
+ cmuclkmsk2 |= MSKCEU;
+ break;
+ case ETHER0_CLOCK:
+ cmuclkmsk2 |= MSKMAC0;
+ break;
+ case ETHER1_CLOCK:
+ cmuclkmsk2 |= MSKMAC1;
+ break;
+ default:
+ break;
+ }
+
+ if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
+ clock == ETHER1_CLOCK)
+ write_cmuclkmsk2();
+ else
+ write_cmuclkmsk();
}
-void vr41xx_clock_mask(u16 mask)
+void vr41xx_clock_mask(unsigned int clock)
{
- cmuclkmsk &= ~mask;
- write_cmu(cmuclkmsk);
+ switch (clock) {
+ case PIU_CLOCK:
+ cmuclkmsk &= ~MSKPIU;
+ break;
+ case SIU_CLOCK:
+ if (current_cpu_data.cputype == CPU_VR4111 ||
+ current_cpu_data.cputype == CPU_VR4121) {
+ cmuclkmsk &= ~(MSKSIU | MSKSSIU);
+ } else {
+ if (cmuclkmsk & MSKDSIU)
+ cmuclkmsk &= ~MSKSSIU;
+ else
+ cmuclkmsk &= ~(MSKSIU | MSKSSIU);
+ }
+ break;
+ case AIU_CLOCK:
+ cmuclkmsk &= ~MSKAIU;
+ break;
+ case KIU_CLOCK:
+ cmuclkmsk &= ~MSKKIU;
+ break;
+ case FIR_CLOCK:
+ cmuclkmsk &= ~(MSKFIR | MSKFFIR);
+ break;
+ case DSIU_CLOCK:
+ if (current_cpu_data.cputype == CPU_VR4111 ||
+ current_cpu_data.cputype == CPU_VR4121) {
+ cmuclkmsk &= ~MSKDSIU;
+ } else {
+ if (cmuclkmsk & MSKSIU)
+ cmuclkmsk &= ~MSKDSIU;
+ else
+ cmuclkmsk &= ~(MSKSIU | MSKDSIU);
+ }
+ break;
+ case CSI_CLOCK:
+ cmuclkmsk &= ~(MSKCSI | MSKSCSI);
+ break;
+ case PCIU_CLOCK:
+ cmuclkmsk &= ~MSKPCIU;
+ break;
+ case HSP_CLOCK:
+ cmuclkmsk &= ~MSKSHSP;
+ break;
+ case PCI_CLOCK:
+ cmuclkmsk &= ~MSKPPCIU;
+ break;
+ case CEU_CLOCK:
+ cmuclkmsk2 &= ~MSKCEU;
+ break;
+ case ETHER0_CLOCK:
+ cmuclkmsk2 &= ~MSKMAC0;
+ break;
+ case ETHER1_CLOCK:
+ cmuclkmsk2 &= ~MSKMAC1;
+ break;
+ default:
+ break;
+ }
+
+ if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
+ clock == ETHER1_CLOCK)
+ write_cmuclkmsk2();
+ else
+ write_cmuclkmsk();
}
-void __init vr41xx_cmu_init(u16 mask)
+void __init vr41xx_cmu_init(void)
{
switch (current_cpu_data.cputype) {
case CPU_VR4111:
case CPU_VR4121:
- vr41xx_cmu_base = VR4111_CMUCLKMSK;
+ vr41xx_cmu_base = CMUCLKMSK_TYPE1;
break;
case CPU_VR4122:
case CPU_VR4131:
- vr41xx_cmu_base = VR4122_CMUCLKMSK;
+ vr41xx_cmu_base = CMUCLKMSK_TYPE2;
+ break;
+ case CPU_VR4133:
+ vr41xx_cmu_base = CMUCLKMSK_TYPE2;
+ cmuclkmsk2 = read_cmuclkmsk2();
break;
default:
panic("Unexpected CPU of NEC VR4100 series");
break;
}
- cmuclkmsk = mask;
+ cmuclkmsk = read_cmuclkmsk();
}
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TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)