patch-2.4.3 linux/arch/ia64/sn/io/pcibr.c
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- Lines: 27
- Date:
Tue Mar 6 19:44:35 2001
- Orig file:
v2.4.2/linux/arch/ia64/sn/io/pcibr.c
- Orig date:
Wed Feb 21 18:20:12 2001
diff -u --recursive --new-file v2.4.2/linux/arch/ia64/sn/io/pcibr.c linux/arch/ia64/sn/io/pcibr.c
@@ -3925,7 +3925,7 @@
* above.
*
* Need to set the D_INTR_ISERR flag
- * in the dev_desc used for alocating the
+ * in the dev_desc used for allocating the
* error interrupt, so our interrupt will
* be properly routed and prioritized.
*
@@ -5540,7 +5540,7 @@
} else
xio_port = pcibr_dmamap->bd_xio_port;
- /* If this DMA is to an addres that
+ /* If this DMA is to an address that
* refers back to this Bridge chip,
* reduce it back to the correct
* PCI MEM address.
@@ -8540,7 +8540,7 @@
*
* CAUTION: Resetting bit BRIDGE_IRR_PCI_GRP_CLR, acknowledges
* a group of interrupts. If while handling this error,
- * some other error has occured, that would be
+ * some other error has occurred, that would be
* implicitly cleared by this write.
* Need a way to ensure we don't inadvertently clear some
* other errors.
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