patch-2.4.3 linux/drivers/net/dmfe.c
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- Lines: 361
- Date:
Tue Mar 20 12:05:01 2001
- Orig file:
v2.4.2/linux/drivers/net/dmfe.c
- Orig date:
Wed Feb 21 18:20:26 2001
diff -u --recursive --new-file v2.4.2/linux/drivers/net/dmfe.c linux/drivers/net/dmfe.c
@@ -127,16 +127,17 @@
#define DMFE_100MFD 5
#define DMFE_AUTO 8
-#define DMFE_TIMER_WUT jiffies+(HZ*2)/2 /* timer wakeup time : 1 second */
+#define DMFE_TIMER_WUT (HZ) /* timer wakeup time : 1 second */
#define DMFE_TX_TIMEOUT ((HZ*3)/2) /* tx packet time-out time 1.5 s" */
-#define DMFE_DBUG(dbug_now, msg, vaule) if (dmfe_debug || dbug_now) printk("DBUG: %s %x\n", msg, vaule)
-
-#define DELAY_5US udelay(5) /* udelay scale 1 usec */
-
-#define DELAY_1US udelay(1) /* udelay scale 1 usec */
-
-#define SHOW_MEDIA_TYPE(mode) printk(KERN_WARNING "dmfe: Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
+#define DMFE_DBUG(dbug_now, msg, value) \
+ if (dmfe_debug || dbug_now) \
+ printk("DBUG: %s %x\n", msg, value)
+
+#define SHOW_MEDIA_TYPE(mode) \
+ printk(KERN_WARNING "dmfe: Change Speed to %sMhz %s duplex\n", \
+ mode & 1 ? "100" : "10", \
+ mode & 4 ? "full":"half");
/* CR9 definition: SROM/MII */
@@ -150,9 +151,17 @@
#define PHY_DATA_0 0x00000
#define MDCLKH 0x10000
-#define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);DELAY_5US;outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);DELAY_5US;outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);DELAY_5US;
-
-#define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
+#define SROM_CLK_WRITE(data, ioaddr) \
+ outl(data | CR9_SROM_READ | CR9_SRCS , ioaddr); \
+ udelay(5); \
+ outl(data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, ioaddr); \
+ udelay(5); \
+ outl(data | CR9_SROM_READ | CR9_SRCS , ioaddr); \
+ udelay(5);
+
+#define __CHK_IO_SIZE(pci_id, dev_rev) \
+ ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? \
+ DM9102A_IO_SIZE : DM9102_IO_SIZE
#define CHK_IO_SIZE(pci_dev, dev_rev) \
__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
@@ -353,9 +362,19 @@
int i;
struct net_device *dev;
u32 dev_rev;
+ u16 pci_command;
DMFE_DBUG(0, "dmfe_probe()", 0);
+ /* Enable Master/IO access, Disable memory access */
+ i = pci_enable_device(pdev);
+ if (i) return i;
+
+ pci_set_master(pdev);
+ pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
+ pci_command &= ~PCI_COMMAND_MEMORY;
+ pci_write_config_word(pdev, PCI_COMMAND, pci_command);
+
pci_iobase = pci_resource_start(pdev, 0);
pci_irqline = pdev->irq;
@@ -372,11 +391,6 @@
goto err_out;
}
- /* Enable Master/IO access, Disable memory access */
- if (pci_enable_device(pdev))
- goto err_out;
- pci_set_master(pdev);
-
#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
/* Set Latency Timer 80h */
@@ -403,7 +417,7 @@
}
db = dev->priv;
- pdev->driver_data = dev;
+ pci_set_drvdata(pdev, dev);
db->chip_id = ent->driver_data;
db->ioaddr = pci_iobase;
@@ -440,7 +454,7 @@
static void __exit dmfe_remove_one (struct pci_dev *pdev)
{
- struct net_device *dev = pdev->driver_data;
+ struct net_device *dev = pci_get_drvdata(pdev);
struct dmfe_board_info *db;
DMFE_DBUG(0, "dmfe_remove_one()", 0);
@@ -451,6 +465,8 @@
release_region(dev->base_addr, CHK_IO_SIZE(pdev, db->chip_revision));
kfree(dev); /* free board information */
+ pci_set_drvdata(pdev, NULL);
+
DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
}
@@ -511,12 +527,12 @@
db->dm910x_chk_mode = 1; /* Enter the check mode */
}
- /* Initilize DM910X board */
+ /* Initialize DM910X board */
dmfe_init_dm910x(dev);
/* set and active a timer process */
init_timer(&db->timer);
- db->timer.expires = DMFE_TIMER_WUT;
+ db->timer.expires = jiffies + DMFE_TIMER_WUT;
db->timer.data = (unsigned long) dev;
db->timer.function = &dmfe_timer;
add_timer(&db->timer);
@@ -526,9 +542,9 @@
return 0;
}
-/* Initilize DM910X board
+/* Initialize DM910X board
Reset DM910X board
- Initilize TX/Rx descriptor chain structure
+ Initialize TX/Rx descriptor chain structure
Send the set-up frame
Enable Tx/Rx machine
*/
@@ -541,7 +557,7 @@
/* Reset DM910x board : need 32 PCI clock to complete */
outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
- DELAY_5US;
+ udelay(5);
outl(db->cr0_data, ioaddr + DCR0);
outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
@@ -559,7 +575,7 @@
db->op_mode = db->media_mode;
dmfe_process_mode(db);
- /* Initiliaze Transmit/Receive decriptor and CR3/4 */
+ /* Initialize Transmit/Receive decriptor and CR3/4 */
dmfe_descriptor_init(db, ioaddr);
/* Init CR6 to program DM910x operation */
@@ -623,10 +639,10 @@
if (db->tx_packet_cnt < TX_MAX_SEND_CNT) {
txptr->tdes0 = 0x80000000; /* set owner bit to DM910X */
db->tx_packet_cnt++; /* Ready to send count */
- outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling comand */
+ outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling command */
} else {
db->tx_queue_cnt++; /* queue the tx packet */
- outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling comand */
+ outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling command */
}
/* Tx resource check */
@@ -654,7 +670,7 @@
/* Reset & stop DM910X board */
outl(DM910X_RESET, ioaddr + DCR0);
- DELAY_5US;
+ udelay(5);
/* deleted timer */
del_timer_sync(&db->timer);
@@ -673,7 +689,7 @@
}
/*
- DM9102 insterrupt handler
+ DM9102 interrupt handler
receive the packet to upper layer, free the transmitted packet
*/
@@ -935,7 +951,7 @@
*/
DMFE_DBUG(0, "Warn!! Warn!! Tx/Rx moniotr step1", db->tx_packet_cnt);
dmfe_dynamic_reset(dev);
- db->timer.expires = DMFE_TIMER_WUT;
+ db->timer.expires = jiffies + DMFE_TIMER_WUT;
add_timer(&db->timer);
return;
}
@@ -990,7 +1006,7 @@
allocated_rx_buffer(db);
/* Timer active again */
- db->timer.expires = DMFE_TIMER_WUT;
+ db->timer.expires = jiffies + DMFE_TIMER_WUT;
add_timer(&db->timer);
}
@@ -999,7 +1015,7 @@
Stop DM910X board
Free Tx/Rx allocated memory
Reset DM910X board
- Re-initilize DM910X board
+ Re-initialize DM910X board
*/
static void dmfe_dynamic_reset(struct net_device *dev)
{
@@ -1027,7 +1043,7 @@
db->wait_reset = 0;
db->rx_error_cnt = 0;
- /* Re-initilize DM910X board */
+ /* Re-initialize DM910X board */
dmfe_init_dm910x(dev);
/* Leave dynamic reser route */
@@ -1123,7 +1139,7 @@
}
/*
- Update CR6 vaule
+ Update CR6 value
Firstly stop DM910X , then written value and start
*/
static void update_cr6(u32 cr6_data, u32 ioaddr)
@@ -1132,14 +1148,14 @@
cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
outl(cr6_tmp, ioaddr + DCR6);
- DELAY_5US;
+ udelay(5);
outl(cr6_data, ioaddr + DCR6);
cr6_tmp = inl(ioaddr + DCR6);
/* printk("CR6 update %x ", cr6_tmp); */
}
/* Send a setup frame for DM9132
- This setup frame initilize DM910X addres filter mode
+ This setup frame initialize DM910X address filter mode
*/
static void dm9132_id_table(struct net_device *dev, int mc_cnt)
{
@@ -1180,7 +1196,7 @@
}
/* Send a setup frame for DM9102/DM9102A
- This setup frame initilize DM910X addres filter mode
+ This setup frame initialize DM910X address filter mode
*/
static void send_filter_frame(struct net_device *dev, int mc_cnt)
{
@@ -1288,10 +1304,10 @@
for (i = 16; i > 0; i--) {
outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
- DELAY_5US;
+ udelay(5);
srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
- DELAY_5US;
+ udelay(5);
}
outl(CR9_SROM_READ, cr9_ioaddr);
@@ -1305,10 +1321,10 @@
static void dmfe_sense_speed(struct dmfe_board_info *db)
{
int i;
- u16 phy_mode;
+ u16 phy_mode = 0;
for (i = 1000; i; i--) {
- DELAY_5US;
+ udelay(5);
phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
if ((phy_mode & 0x24) == 0x24)
break;
@@ -1429,11 +1445,11 @@
phy_write_1bit(ioaddr, PHY_DATA_0);
phy_write_1bit(ioaddr, PHY_DATA_1);
- /* Send Phy addres */
+ /* Send Phy address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
- /* Send register addres */
+ /* Send register address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
@@ -1476,11 +1492,11 @@
phy_write_1bit(ioaddr, PHY_DATA_1);
phy_write_1bit(ioaddr, PHY_DATA_0);
- /* Send Phy addres */
+ /* Send Phy address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
- /* Send register addres */
+ /* Send register address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
@@ -1503,11 +1519,11 @@
static void phy_write_1bit(u32 ioaddr, u32 phy_data)
{
outl(phy_data, ioaddr); /* MII Clock Low */
- DELAY_1US;
+ udelay(1);
outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
- DELAY_1US;
+ udelay(1);
outl(phy_data, ioaddr); /* MII Clock Low */
- DELAY_1US;
+ udelay(1);
}
/*
@@ -1518,10 +1534,10 @@
u16 phy_data;
outl(0x50000, ioaddr);
- DELAY_1US;
+ udelay(1);
phy_data = (inl(ioaddr) >> 19) & 0x1;
outl(0x40000, ioaddr);
- DELAY_1US;
+ udelay(1);
return phy_data;
}
@@ -1570,7 +1586,7 @@
/* Description:
* when user used insmod to add module, system invoked init_module()
- * to initilize and register.
+ * to initialize and register.
*/
static int __init dmfe_init_module(void)
@@ -1599,12 +1615,10 @@
rc = pci_module_init(&dmfe_driver);
if (rc < 0)
return rc;
- if (rc >= 0) {
- printk (KERN_INFO "Davicom DM91xx net driver loaded, version "
- DMFE_VERSION "\n");
- return 0;
- }
- return -ENODEV;
+
+ printk (KERN_INFO "Davicom DM91xx net driver loaded, version "
+ DMFE_VERSION "\n");
+ return 0;
}
/*
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)