patch-2.4.5 linux/arch/cris/lib/dram_init.S

• Lines: 179
• Date: Tue May 1 16:04:56 2001
• Orig file: v2.4.4/linux/arch/cris/lib/dram_init.S
• Orig date: Fri Apr 6 10:42:55 2001

diff -u --recursive --new-file v2.4.4/linux/arch/cris/lib/dram_init.S linux/arch/cris/lib/dram_init.S
@@ -1,63 +1,97 @@
-	;; $Id: dram_init.S,v 1.2 2001/02/08 15:20:00 starvik Exp $
-	;; 
-	;; DRAM/SDRAM initialization - alter with care
-	;; This file is intended to be included from other assembler files
-	;;
-	;; Copyright (C) 2000 Axis Communications AB
-	;;
-	;; Authors:  Mikael Starvik (starvik@axis.com)	
-	;;           Bjorn Wesen (bjornw@axis.com)
-	;; 
-	;; $Log: dram_init.S,v $
-	;; Revision 1.2  2001/02/08 15:20:00  starvik
-	;; Corrected SDRAM initialization
-	;; Should now be included as inline
-	;;
-	;; Revision 1.1  2001/01/29 13:08:02  starvik
-	;; Initial version
-	;; This file should be included from all assembler files that needs to
-	;; initialize DRAM/SDRAM.
-	;;
-	;;
-	;;
+/* $Id: dram_init.S,v 1.7 2001/04/18 12:05:39 bjornw Exp $
+ * 
+ * DRAM/SDRAM initialization - alter with care
+ * This file is intended to be included from other assembler files
+ *
+ * Note: This file may not modify r9 because r9 is used to carry
+ *       information from the decompresser to the kernel
+ *
+ * Copyright (C) 2000, 2001 Axis Communications AB
+ *
+ * Authors:  Mikael Starvik (starvik@axis.com)	
+ * 
+ * $Log: dram_init.S,v $
+ * Revision 1.7  2001/04/18 12:05:39  bjornw
+ * Fixed comments, and explicitely include config.h to be sure its there
+ *
+ * Revision 1.6  2001/04/10 06:20:16  starvik
+ * Delay should be 200us, not 200ns
+ *
+ * Revision 1.5  2001/04/09 06:01:13  starvik
+ * Added support for 100 MHz SDRAMs
+ *
+ * Revision 1.4  2001/03/26 14:24:01  bjornw
+ * Namechange of some config options
+ *
+ * Revision 1.3  2001/03/23 08:29:41  starvik
+ * Corrected calculation of mrs_data
+ *
+ * Revision 1.2  2001/02/08 15:20:00  starvik
+ * Corrected SDRAM initialization
+ * Should now be included as inline
+ *
+ * Revision 1.1  2001/01/29 13:08:02  starvik
+ * Initial version
+ * This file should be included from all assembler files that needs to
+ * initialize DRAM/SDRAM.
+ *
+ */
+
+/* Just to be certain the config file is included, we include it here
+ * explicitely instead of depending on it being included in the file that
+ * uses this code.
+ */
 
 #include <linux/config.h>
 
+
 #ifndef CONFIG_SVINTO_SIM	
-	move.d   DEF_R_WAITSTATES, r0
+	move.d   CONFIG_ETRAX_DEF_R_WAITSTATES, r0
 	move.d   r0, [R_WAITSTATES]
 
-	move.d   DEF_R_BUS_CONFIG, r0
+	move.d   CONFIG_ETRAX_DEF_R_BUS_CONFIG, r0
 	move.d   r0, [R_BUS_CONFIG]
 	
-#ifndef CONFIG_SDRAM
-	move.d   DEF_R_DRAM_CONFIG, r0
+#ifndef CONFIG_ETRAX_SDRAM
+	move.d   CONFIG_ETRAX_DEF_R_DRAM_CONFIG, r0
 	move.d   r0, [R_DRAM_CONFIG]
 
-	move.d   DEF_R_DRAM_TIMING, r0
+	move.d   CONFIG_ETRAX_DEF_R_DRAM_TIMING, r0
 	move.d   r0, [R_DRAM_TIMING]
 #else	
 	; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
 	
 	; Bank configuration
-        move.d   DEF_R_SDRAM_CONFIG, r0
+	move.d   CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, r0
 	move.d   r0, [R_SDRAM_CONFIG]
 
 	; Calculate value of mrs_data 
-	; cas_delay = 2 && bus_width = 32 => 0x40
-	; cas_delay = 3 && bus_width = 32 => 0x60
-	; cas_delay = 2 && bus_width = 16 => 0x20
-	; cas_delay = 3 && bus_width = 16 => 0x30
+	; CAS latency = 2 && bus_width = 32 => 0x40
+	; CAS latency = 3 && bus_width = 32 => 0x60
+	; CAS latency = 2 && bus_width = 16 => 0x20
+	; CAS latency = 3 && bus_width = 16 => 0x30
 	
-	move.d   0x40, r2       ; Assume 32 bits and cas_delay = 2
-	move.d   DEF_R_SDRAM_TIMING, r1
-	and.d    0x0c, r1	; Get cas delay
-	cmp.d    0x08, r1	; cas_delay = 2?
-        beq      bw_check
+	move.d   0x40, r2       ; Assume 32 bits and CAS latency = 2
+	move.d   CONFIG_ETRAX_DEF_R_SDRAM_TIMING, r1
+	move.d   r1, r3
+ 	and.d    0x03, r1       ; Get CAS latency
+	and.d    0x1000, r3     ; 50 or 100 MHz?
+	beq      speed_50
+	nop
+speed_100:		
+	cmp.d    0x00, r1	; CAS latency = 2?
+	beq      bw_check
+	nop
+	or.d     0x20, r2	; CAS latency = 3 
+	ba       bw_check
+	nop
+speed_50:			
+	cmp.d    0x01, r1	; CAS latency = 2?
+	beq      bw_check
 	nop
-	or.d     0x20, r2       ; cas_delay = 3
+	or.d     0x20, r2       ; CAS latency = 3
 bw_check:
-	move.d   DEF_R_SDRAM_CONFIG, r1
+	move.d   CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, r1
 	and.d    0x800000, r1	; DRAM width is bit 23
 	bne      set_timing
 	nop
@@ -65,14 +99,17 @@
 
 	; Set timing parameters. Starts master clock
 set_timing:
-	move.d   DEF_R_SDRAM_TIMING, r1
+	move.d   CONFIG_ETRAX_DEF_R_SDRAM_TIMING, r1
+	and.d    0x8000f9ff, r1 ; Make sure mrs data and command is 0 
 	or.d     0x80000000, r1	; Make sure sdram enable bit is set
+	move.d   r1, r5
+	or.d     0x0000c000, r1 ; ref = disable
 	lslq     16, r2		; mrs data starts at bit 16
 	or.d     r2, r1 
 	move.d   r1, [R_SDRAM_TIMING]	
 		
-	; Wait 200ns
-	move.d   10, r2
+	; Wait 200us
+	move.d   10000, r2
 sdram_loop:
 	bne      sdram_loop
 	subq     1, r2
@@ -83,10 +120,10 @@
 command_loop:
 	clear.d  r4
 	move.b   [r2+], r4
-	lslq     9, r4		; Command starts at bit 9
+	lslq     9, r4	; Command starts at bit 9
 	or.d     r1, r4
 	move.d   r4, [R_SDRAM_TIMING]
-	nop			; Wait five nop cycles between each command
+	nop		; Wait five nop cycles between each command
 	nop
 	nop
 	nop
@@ -94,6 +131,7 @@
 	cmp.d    r2, r3
 	bne      command_loop
 	nop
+	move.d   r5, [R_SDRAM_TIMING]
 	ba       sdram_commands_end
 	nop