patch-2.4.6 linux/include/asm-mips/bcache.h
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- Lines: 63
- Date:
Mon Jul 2 13:56:40 2001
- Orig file:
v2.4.5/linux/include/asm-mips/bcache.h
- Orig date:
Sat May 13 08:31:25 2000
diff -u --recursive --new-file v2.4.5/linux/include/asm-mips/bcache.h linux/include/asm-mips/bcache.h
@@ -1,14 +1,19 @@
-/* $Id$
- *
+/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (c) 1997, 1999 by Ralf Baechle
+ * Copyright (c) 1997, 1999, 2000 by Ralf Baechle
+ * Copyright (c) 2000 by Silicon Graphics, Inc.
*/
#ifndef _ASM_BCACHE_H
#define _ASM_BCACHE_H
+#include <linux/config.h>
+
+/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
+ chipset implemented caches. On machines with other CPUs the CPU does the
+ cache thing itself. */
struct bcache_ops {
void (*bc_enable)(void);
void (*bc_disable)(void);
@@ -19,6 +24,39 @@
extern void indy_sc_init(void);
extern void sni_pcimt_sc_init(void);
+#ifdef CONFIG_BOARD_SCACHE
+
extern struct bcache_ops *bcops;
+
+extern inline void bc_enable(void)
+{
+ bcops->bc_enable();
+}
+
+extern inline void bc_disable(void)
+{
+ bcops->bc_disable();
+}
+
+extern inline void bc_wback_inv(unsigned long page, unsigned long size)
+{
+ bcops->bc_wback_inv(page, size);
+}
+
+extern inline void bc_inv(unsigned long page, unsigned long size)
+{
+ bcops->bc_inv(page, size);
+}
+
+#else /* !defined(CONFIG_BOARD_SCACHE) */
+
+/* Not R4000 / R4400 / R4600 / R5000. */
+
+#define bc_enable() do { } while (0)
+#define bc_disable() do { } while (0)
+#define bc_wback_inv(page, size) do { } while (0)
+#define bc_inv(page, size) do { } while (0)
+
+#endif /* !defined(CONFIG_BOARD_SCACHE) */
#endif /* _ASM_BCACHE_H */
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