+------------------------------------------------------------+
|                                                            |
| a) What will be in the ROM in the "off the shelf" devices? |
| b) How do you handle memory access speed hierarchy such    |
| as EPROM and RAM for Program memory?                       |
|                                                            |
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Answer:

a) The DSP56001 has positive MU/A Law tables in X-Data ROM and a
   256-point full Sine table in Y-Data ROM. For more information
   please refer to the BR505 document.
 
b) Memory access speed hierarchy  (also see answer a21)

     1) On chip it is fixed, no wait states.

     2) External - One of the four nibbles in the BCR ( Bus 
        Control Register ) sets the number of wait states
        inserted when accessing external program memory. The
        remaining three nibbles in the BCR set the number of wait
        states for X and Y data memories and locations in
        peripheral memory space. When overlaying from an external
        EPROM the BCR can be programmed to add wait states. Once
        the overlay has been completed the BCR can be programmed
        to reduce the number of wait states to support accesses to
        the external RAM. Naturally every effort should be made
        to execute from the on-chip program RAM which has just
        been overlayed.
