+-----------------------------------------------------------------------------+
|  "Why did you use separate RD and WR signals on the 56000/1 instead of the  | 
|  familiar R/W and Enable signals?"                                          | 
+-----------------------------------------------------------------------------+

The 56000/1 was designed for "direct connect" to fast static RAM's.  The RD
signal can be directly connected to the RAM output enable (OE) input and the
WR signal can be directly connected to the RAM write enable (WR) input. The 
RAM chip select (CS) is derived directly from the program or data strobe (PS
or DS).  A second RAM chip select can be driven by the X/Y signal, if desired.
This allowed zero wait state operation with 55 nsec RAM's using a 97.5 nsec
instruction rate at 20.5 MHz.  The separate read and write strobes are mutually
exclusive with a guard time between them to avoid two data buffers from being
enabled at the same time.  Other methods using external logic gates to generate
the RAM control inputs require either faster RAM chips or external data buffers
to avoid data bus buffer conflicts.  As faster 56000/1's are introduced,
external logic delay is large relative to RAM timing margins, making the design
more difficult.
 
There is an easy way to interface with 6800 and 68000 peripherals and to have 
an early read/write indication.  The trick is to use the X/Y output pin as an 
early R/W indication.  The peripheral chip select should be derived from the 
address lines and the data strobe such that the peripheral registers show up in 
both X and Y data memory spaces at the same addresses.  For a read operation, 
perform an X memory read
 
	move x:peripheral,x0           ;X/Y signal is high.
 
For a write operation, perform a Y memory write
 
	move x0,y:peripheral           ;X/Y signal is low.
 
Since the X/Y output signal has the same timing as the address lines, it 
provides an early read/write indication.  The RD and WR signals are ANDed 
together to form a "data strobe" signal.  The only restriction is that X and Y 
memory space must be external at the same address.  This means that the I/O 
Short addressing mode and the MOVEP instruction cannot be used for this 
application.  Otherwise, the hardware and software are trivial.
 
The DSP96002 has an early R/W signal because its bus control signals are
optimized for dynamic and video RAM's, which need an early write indication.
