Stradis Professional MPEG-2 Decoder EEPROM Definition
August 11, 1999


Introduction
The Stradis Professional Decoder contains an I2C EEPROM that is used to store information about 
available (installed) resources on the card. It also provides information about nominal levels for systems 
like the VCXO and 0db level for the analog audio output. This document defines how the EEPROM is 
organized to provide this information.
EEPROM Size and Address
The EEPROM contains 128 bytes of data. The EEPROM is located in the I2C address space at 0x20 
(0010000m where ‘m’ is the read/write bit). Bytes 0-5 are used by the PCI bridge to initialize six bytes in 
the PCI configuration space. The other 122 bytes are used to store information about installed components 
and nominal levels. Bytes 0-63 are defined by this document. The remaining 64 bytes are reserved for 
future or customer use. Bytes 0-5 should contain the following information 
{0x00,0x01,0x04,0x13,0x26,0x0f}.
EEPROM Organization
The information about installed components, serial number, manufacture date, etc. are stored in the 
EEPROM starting at address offset 6. The various data fields in the EEPROM are stored most significant 
byte first. The data fields have a variable length. Byte 63 contains a checksum on the first 63 bytes of the 
EEPROM. This byte can be used to validate the EEPROM contents. The checksum is calculated as the 
negative of the sum of the bytes 0-62. Therefore, adding bytes 0-63 should result in a value of zero if the 
data in the EEPROM is valid.
EEPROM Structure Revision (byte 6)
This single-byte field indicates the revision of the PROM structure. The upper 4 bits are the major revision 
and the lower four bits are the minor revision. Minor revisions add fields to the end of the structure without 
changing the beginning of the structure. Major revisions change the structure of all of the PROM.
Serial Number (bytes 7 – 9)
This three-byte field contains the serial number of the board.
Manufacturing Plant (byte 10)
This is a one-byte field. Values 0-127 are reserved for in house use. Values 128 through 255 are reserved 
for outside contract manufacturers. Value 0 indicates an engineering prototype.
Manufacturing Year (byte 11)
This one-byte field indicates the year in which the board was manufactured. The value of this field must be 
added to 1900 to get the actual year.
Manufacturing Week (byte 12)
This one-byte filed indicates the week of the year in which the board was manufactured. Values are 1 
through 52.
PWM Nominal Setting (bytes 13, 14)
This two-byte field is used to indicate the nominal setting that will provide a 27MHz-reference frequency 
when using the PWM mode of the clock generator. Valid values are 0 to 1023. This value should be placed 
in the PWM control register.
PWM Gain Factor (bytes 15, 16)
This two-byte field is used to indicate the gain factor of PWM circuit. The measurement is in PPM per 
increment of the PWM control register. The Gain Factor value is organized as a fractional value. The upper 
byte is the integer part and the lower byte is the fractional part.
Installed Components (bytes 17, 18)
This two-byte field is used to indicate what components are installed. The bits are defined as follows:
Bit 0 (byte 18)
One if CS3310 is installed, zero if not.
Bit 1
One if the Balanced Drivers are install, zero if not. The balanced output level is the single end output level 
plus the gain difference between the single ended output and the balanced output.
Bit 2
One if the CS8240 (AES3) is installed, zero if not.
Bit 3
One if the Microlinear Video Filter is installed, zero if not.
Bit 4
One if second FPGA is installed, zero if not.
Bit 5
One if CD20, zero if CD21
Bit 6
One if 2MB of memory, Zero if 4 MB of memory
Bit 7
One if ProgramDone signal on FPGA can be read on GPIO1, zero if not.
DV FPGA Filename (bytes 19-26)
This eight-byte field is the name of the file to be loaded into the DV FPGA. The actual name requires the 
“Filename” be appended with a “.bit” extension. If the Filename starts with a null byte, no file is to be 
loaded into the DV FPGA (i.e. the DV FPGA is not installed).
Digital Video Type (byte 27)
This one-byte field indicates what type digital video chip set is being used.
Cypress Full Chip Set (Type 1)
This indicates that both the serializer and the scrambler are present.
Cypress Serializer Only (Type 2)
This indicates that the scrambler must be performed in the second FPGA as only the Serializer is present in 
the DV chain.
Audio Analog Output Minimum Level Setting (bytes 28, 29)
This two-byte field contains the minimum allowable value for the volume control.
Audio Analog Output Maximum Level Setting (bytes 30, 31)
This two-byte field contains the maximum allowable value for the volume control.
Audio Analog Output Full Scale Minimum Level (bytes 32, 33)
This two-byte field contains the output level in dBu when the output is set to the minimum level. The two 
bytes represent a fractional number with the upper byte being the integer and the lower byte being the 
fraction. This value is for the single-ended output.
Audio Analog Output Full Scale Maximum Level (bytes 34, 35)
This two-byte field contains the output level in dBu when the output is set to the maximum level assuming 
there is not power supply limitation. The two bytes represent a fractional number with the upper byte being 
the integer and the lower byte being the fraction. This value is for the single-ended output.
Audio Analog Output Balanced Gain Difference (bytes 36, 37)
This two-byte field contains the gain difference between the single ended output and the balanced output 
level in dBu. The two bytes a fractional number with the upper byte being the integer and the lower byte 
being the fraction.
Audio Analog Output Maximum Level (bytes 38, 39)
This two-byte field contains the typical maxim output level in dBu before power supply saturation occurs. 
The two bytes represent a fractional number with the upper byte being the integer and the lower byte being 
the fraction. This value is for the single-ended output.
DAC Type (byte 40)
This one-byte field indicates what DAC is used on the board.
CS4331 (Type 1)
This DAC has no controls. The De-emphasis circuit is controlled by the output of the IBM MPEG Decoder 
Chip.
CS4341 (Type 2)
This DAC has an I2C interface for controlling the DAC. The I2C address is 0x22. The De-emphasis circuit 
is controlled through the I2C interface not by the output signal from the IBM MPEG decoder. This DAC 
also contains a digital volume control. The volume control has 24 bits of resolution, so effectively no re-
quantization error results from using the volume control. However, the DAC noise floor remains the same 
regardless of this volume control setting, so using the on-board analog based volume control (CS3310) is 
preferable to either the volume control in the CS4341 or the volume control in the IBM MPEG decoder 
chip. The volume control in the IBM MPEG decoder should be used on if the board does not contain the 
C3310 or the CS4341.
DENC Type (byte 41)
This one-byte field indicates Digital Video Encoder (DENC) is used on the board.
SAA7120 (Type 1)
SAA7121 (Type 2)
Main FPGA Filename (bytes 42 – 49)
This eight-byte field is the name of the file to be loaded into the Main FPGA. The actual name requires the 
“Filename” be appended with a “.bit” extension. If the Filename starts with a null byte, the filename is 
assumed to be decxl.bit.
Board Revision (byte 50)
This one-byte field indicates the copper revision of the board.

